Use a default priority to avoid Kconfig blocking when priority
is not set in SoC or Board.
Change-Id: I4edda47b955a7ee834f04dc40d0decbd8dee6305
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Put initialization priorities as device driver Kconfig
parameter.
Initialization priority value for each platform is defined
in the platform Kconfig file.
Drivers and platform code use SYS_DEFINE_DEVICE to add
and initialization function.
Change-Id: I2f4f3c7370dac02408a1b50a0a1bade8b427a282
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The kernel configuration option SHARED_IRQ_1_PRI is dependent upon
SHARED_IRQ_1, not SHARED_IRQ_0.
Change-Id: I018cd8e860c362572cdde8586e50aed990d350bc
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the default IRQ priority level from 0 to 2 for the following
kernel configuration options as priorities 0 and 1 are reserved for the
first 32 IDT entries.
SHARED_IRQ_0_PRI
SHARED_IRQ_1_PRI
I2C_DW_0_INT_PRIORITY
GPIO_DW_0_PRI
GPIO_DW_1_PRI
SPI_INTEL_PORT_0_PRI
SPI_INTEL_PORT_1_PRI
Change-Id: I0fc821c68156eb1e1fe776b2bd4ff5890bba40e8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This adds options to the shared IRQ driver so the interrupt
triggering condition can be specified.
For example, the GPIO and I2C controllers are under same
interrupt line through PCI bus. The triggering condition
is level, active-low. So this option can be used by
the Galileo platform to program the IO-APIC correctly.
Change-Id: I1c3af98442e775b4987ab36a644c856052d85ec4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This driver allows multiple drivers to share a common interrupt
line. This functionality is required on system that conform to the PC
interrupt structure. In the context of Zephyr this is needed for
SOC's that have their I/O IP blocks behind a PCI interface. Due to the
limited number of interrupt lines provided by the PCI interface
multiple IP blocks may be configured to share an interrupt line.
Drivers that share interrupts must be modified to *not* register their
own interrupt service routine as part of their configuration/initialization
but instead bind to the correct instance of this driver by name, then
register their interrupt service routine with this driver.
Change-Id: I57b517b97ebeabce484ba53c8f940da993cb391d
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Anas Nashif