zephyr

Commit Graph

Author	SHA1	Message	Date
Karsten Koenig	2e61137cc9	arch: riscv: thread: Init soc context on stack The optional SOC_CONTEXT carries processor state registers that need to be initialized properly to avoid uninitialized memory read as processor state. In particular on the RV32M1 the extra soc context stores a state for special loop instructions, and loading non zero values will have the core assume it is in a loop. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>	2020-07-13 15:00:19 -05:00
Kumar Gala	a1b77fd589	zephyr: replace zephyr integer types with C99 types git grep -l 'u\(8\\|16\\|32\\|64\)_t' \| \ xargs sed -i "s/u\(8\\|16\\|32\\|64\)_t/uint\1_t/g" git grep -l 's\(8\\|16\\|32\\|64\)_t' \| \ xargs sed -i "s/s\(8\\|16\\|32\\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>	2020-06-08 08:23:57 -05:00
Nicolas Pitre	1f4b5ddd0f	riscv32: rename to riscv With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>	2019-08-02 13:54:48 -07:00

Author

SHA1

Message

Date

Karsten Koenig

2e61137cc9

arch: riscv: thread: Init soc context on stack

The optional SOC_CONTEXT carries processor state registers that need to
be initialized properly to avoid uninitialized memory read as processor
state.
In particular on the RV32M1 the extra soc context stores a state for
special loop instructions, and loading non zero values will have the
core assume it is in a loop.

Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>

2020-07-13 15:00:19 -05:00

Kumar Gala

a1b77fd589

zephyr: replace zephyr integer types with C99 types

git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

2020-06-08 08:23:57 -05:00

Nicolas Pitre

1f4b5ddd0f

riscv32: rename to riscv

With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

2019-08-02 13:54:48 -07:00

3 Commits