Commit Graph

10 Commits

Author SHA1 Message Date
Max Filippov 59926490be xtensa: move #include <linker/common-*.ld> up
Move linker/common-rom.ld between .rodata sections so that it's together
with other immutable data.
Move linker/common-ram.ld before the .bss section, so that .bss does not
appear between data sections, which had two consequences:
- there's a .bss-sized gap in the ELF image, and
- PHDR segment that covers .bss overlaps the segment that covers .data,
  resulting in the following xt-run warning:

  ( [ sample_controller ] load_bfd ) *WARNING* Executable segment
    [ 60004d60, 600079a7 ] overlaps an existing executable segment

Change-Id: I2db46f4656e240016fe60883057cc000b6377180
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-04-20 16:01:18 +00:00
Andrew Boie 11ee791b32 xtensa: build similar to other Zephyr arches
* CONFIG_SOC is now properly set and we do not need a separate
  XTENSA_CORE build variable

* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed

* There is no default SOC selection, it is now done explicitly in
  the board's defconfig

* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
  uppercase> to conform to established style.

Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-13 12:42:06 +00:00
Mazen NEIFER 3b95e3d729 Xtensa port: Added support for sample_controller core and set is as default.
This core is not depreciated and compilationfor it is even faster than D_233L.

Change-Id: I6b8149ca9e879770c3ed0973ffb9304e2e3c8d8d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER 6af2778136 Xtensa port: Fixed linker script for hifi_mini core.
Change-Id: I21f4ff0c136c1e72e6d36d179898bbde1b08b71f
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER cb745e6047 Xtensa port: Fixed RAMABLE_REGION in linker scripts.
This was introduced during a copy/paste when updating patch
https://gerrit.zephyrproject.org/r/#/c/10323/6..7

Change-Id: Id6857dd28a16974361932285b44559f702c4d910
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER af2593ea7e Xtensa port: Added linker script for several Xtensa cores.
Change-Id: I7a40d5f0c3fe8d25623b88f06523cb62e4ba4706
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER e2dd006ba7 Xtensa port: Removed the need to put an empy file soc.c in arch/xtensa/soc dir.
Change-Id: I439a6c36f10c6255d15a688c8f425de0fab93912
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Andrew Boie aa3ab35c88 xtensa: fixup license identifiers
Master branch changed requirements for license headers while this
branch has been in development.

Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Max Filippov f5f69c99c4 xtensa: support 'make qemu' target
Provide generic support for running zephyr kernels on xtensa QEMU and
map D_233L SoC to dc233c QEMU core.

Change-Id: Ie804588f750213a7cc54dbc95c86ee4d62ba1ea5
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 1cded67f38 Xtensa port: Started port to for Xtensa cores family.
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.

Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:26 -08:00