Commit Graph

10 Commits

Author SHA1 Message Date
Daniel Maslowski 6b495ceda9 dts: jh7110: fix memory definitions
The L2LIM is 2MB in size, see:
https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/u74_memory_map.html
Rename it since there are other memory blocks such as the DTIM for the S7.

Signed-off-by: Daniel Maslowski <info@orangecms.org>
2024-04-09 14:20:39 +02:00
Pratik Farkase 7679b8e6b4 dts: riscv: starfive: add DT includes for JH7110 SOC
These list of files add basic support for StarFive
JH7110 SOC Device Tree includes for VisionFive2
board.

Signed-off-by: Pratik Farkase <pratik.farkase@wsisweden.com>
2024-03-13 11:39:51 -05:00
Filip Kokosinski 17670be2cc dts/riscv: remove the `timebase-frequency` property
The `timebase-frequency` is not defined by any of the YAML binding files.
There was a discussion in #37420 to add this property, but in the end it
was rejected. This resulted in the #37685 feature request being created.

As of now, this property is not documented anywhere so this commit removes
it from the RISC-V devicetrees, as RISC-V is the only architecture that is
currently defining it - and even in RISC-V not all platforms do that.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Yong Cong Sin 39433f0669 drivers: intc: plic: define all registers' offset in the driver
Define all the register offset directly in the driver according
to the RISCV PLIC specification as they are not configurable,
see: https://github.com/riscv/riscv-plic-spec.

Updated devicetrees that has PLIC accordingly.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-10-04 09:06:28 -04:00
Filip Kokosinski 806c95163a dts/riscv: add missing `riscv,isa` fields and modify existing ones
This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
  D extension implies the F extension, so writing `rv32ifd` is redundant

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-09-14 14:34:34 +02:00
Gerard Marull-Paretas af2f5753d8 dts: riscv: starfive: align clint description with Linux
The CLINT (Core Local Interruptor) description was not aligned with
Linux. For example, there's no "riscv,clint0", but "sifive,clint0". The
peripheral is not described as an interrupt-controller either.

Ref. https://elixir.bootlin.com/linux/v5.18.14/source/arch/riscv/boot/
dts/starfive/jh7100.dtsi#L106

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Kumar Gala b385afb6fd dts: riscv: Remove label property from devicetrees
Label properties are not required.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 12:57:23 -05:00
Olof Johansson 07ac630281 dts: riscv: add #address-cells to all interrupt controllers
This mirrors #36499 and other PRs that added them for other
architectures.

This silences a large number of dtc warnings due to the missing
property. It seems reasonable to require an address-cells property since
any interrupt controller could be the parent of an interrupt-map.

The only device actually using interrupt-maps is neorv32, and it needs
an address-cells of 2 (since this is the default if none is specified it
worked like that before this change).

While I touched this, I reordered the properties for consistency across
boards, but there's a lot of variance here already.

Signed-off-by: Olof Johansson <olof@lixom.net>
2022-07-04 14:39:43 -04:00
Gerard Marull-Paretas 0d85931315 dts: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:54:54 +02:00
Rajnesh Kanwal 1c584127ba boards: risc-v: add BeagleV Starlight JH7100 board support
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
2021-06-22 08:45:00 -04:00