The toolchain headers included an abstraction for defining symbol
names in assembly context in the situation where we're using a
DOS-style assembler that automatically prepends an underscore to
symbol names.
We aren't. Zephyr is an ELF platform. None of our toolchains do
this. Nothing sets the "TOOL_PREPENDS_UNDERSCORE" macro from within
the project, and it surely isn't an industry standard. Yank it out.
Now we can write assembler labels in natural syntax, and a few other
things fall out to simplify too.
(NOTE: these headers contain assembly code and will fail checkpatch.
That is an expected false positive.)
Change-Id: Ic89e74422b52fe50b3b7306a0347d7a560259581
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is at the expense of code size. The QEMU and MAX10
targets have plenty of space so enable it for these boards,
but leave off by default for others.
Change-Id: I93fdb7db14232727e9953b22490d8869ff3b60e7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The code expected r10 to be preserved across the call to the
event logger, which wasn't reasonable given that it is caller-
saved.
Change-Id: I694357ea7ee9b410b93b5a0894e8c38c53127363
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now allow use of -mgpopt=global and -mgpopt=data. The 'global'
option is now the default instead of compiler-default local, expanding
global pointer usage to all small data in the system.
For systems where all RAM is less than 64K, the 'data' option may be
appropriate.
Some fixes had to be made to the system in order to get around some
issues:
* prep_c.c no longer uses fake linker variables to figure out the size
of data or BSS, as these gave the linker fits as it tried to compute
relative addresses to them.
* _k_task_ptr_idle is create by sysgen and placed in a special section.
Any small data in a special section needs to be declared extern
with __attribute__((section)) else the compiler will assume it's in
.sdata.
* same situation with extern references to k_pipe_t (fixed pipe_priv
test)
For legacy applications being ported to Nios II which do things that
freak out global pointer calculation, it can be disabled entirely.
Change-Id: I5eb86ee8aefb8e2fac49c5cdd104ee19cea23f6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
needs to be 0x8000 after .sdata and .sbss sections since
register offsets are 16-bit signed values.
Change-Id: Ia7486d32af81e54a6ebac6be7ec308dfdeafe79e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The caches get initialized on boot and flushed after XIP copy
takes place.
Change-Id: I642a14232835a0cf41e007860f5cdb8a2ade1f50
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Interrupts and context switches are logged. Since this CPU does not
have a power-saving instruction, it never enters a sleep state so
we do not call _sys_k_event_logger_enter_sleep() from anywhere.
Change-Id: Idcef388e93ffea373446997a0f87e93a4db44331
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Interrupts must always be unlocked when coming out of this function
or execution will never leave _power_save() once entered.
Change-Id: Idda9d9be7cfc576a1072afec38000f63ae262a10
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We are not going to handle unimplemented math instruction
exceptions at runtime. Remove remaining comments and exports
related to this. We don't need to leave a gap in the exception
stack frame for it either.
Change-Id: I4f1f3980a0e43bbf6f2f7488a9182f7acb06be05
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Before we were hard-coding them in the assembly file. Makes it
easier to alter the layout of the struct.
Change-Id: I619dc67c68ff87fe60de429a69b2f604292d270c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The faulting instruction was off by 4 bytes and we weren't printing
the exception cause code properly.
Change-Id: I86f4320c7be43dca96940186def56aa5e47bc49f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We want to pass along the stack pointer, not dereference it.
Change-Id: I554eff316bffe50654942746e7960b561abb413b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Pulled from the ARC implementation. Tested via
test_obj_tracing.
Change-Id: I858e89cc9187f99539b362ade8098b3606d31464
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Unnecessary and generates build errors for microkernel.
Change-Id: I678f44aa2b68c8f8954c78e7828e534f0c1f4215
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Nios II CPUs vary in configuration on whether they support
'mul', 'mulx', and 'div' family of instructions. The compiler
can be told to use GCC integer library routines instead if
needed.
Ideally we would just pull the configuration out of system.h,
but pulling include file #defines into the Make environment
will involve some build system work that is best left to a
later improvement.
We've decided to take this build-time approach rather than
handle unimplemented instruction exceptions, so remove the
hook in exception.S
Change-Id: I05be0d5ed4c1a49b23dca1550ee66fd5891044d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
If the CPU lacks certain features the only writable bit in the
status register is the PIE bit, so just write the saved value back.
Change-Id: I91537ff640aa9977d19587c4b0ae414028752341
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The return value of _Swap() is often treated as a "don't care" value and thus
often ignored. However, there are cases when it is desirable to have a
meaningful return value. This meaningful value can be assigned via
fiberRtnValueSet(). To that end, a new field has been added to the coop
register struct to store this value for when _Swap() needs to return that
meaningful value.
Change-Id: Ic4967fa7d602850c09ebde18e8bfd4c97cda9ec8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For this implementation, the presence of a value in global
_offload_routine signifies to the exception code that we should
enter the IRQ handling code even if there are no bits enabled
in ipending. The 'trap' instruction gets us into the exception
handling code.
Change-Id: Iac96adba0eaf24b54ac28678a31c26517867a4d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.
Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
With this code we can successfully boot and context switch into
the main thread. Nanokernel hello_world has the expected
"Hello World!" string in the RAM console.
Change-Id: I56335d992f5a7cbb12d9e4c02d1cc23ea28ae6ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
When an image is sent over the wire with the GDB 'load' command,
it tries to start execution from the __start symbol, which needs to
be in RAM. Since the reset vector is in ROM, name it something else.
Change-Id: Id0bbfa76db9a8a81bd7ff20be3f2baec81eae15e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Kconfig doesn't enforce any kind of alignment when specifying the
ISR stack size. Perform the assembly equivalent of STACK_ROUND_DOWN.
Change-Id: Ib7fb72ff7db8a3aa20ec6d0c59a03aa8227f6671
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
CONFIG_INIT_STACKS should initialize all stack regions
with 0xaa. Make sure the initial interrupt stack gets this
as well. Take care not to exceed the bounds of the array
if it is not 4-byte aligned.
Change-Id: Ib23329ac84a5a8515272be2944f948e8faba65b3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Nios II does not have a power saving instruction, so there is nothing
to really do here other than ensure that interrupts are in the correct
state when leaving nano_cpu_atomic_idle().
Change-Id: I664c7542dc2fc1795a453d35e183a737dcb20c38
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
__start is the CPU's reset vector. In a typical Nios II configuration,
the exception vector is 0x20 bytes after the reset vector, severely
constraining the amount of code that can go in here.
Split this into __start and __text_start. The only thing that __start
really need to do is init the instruction cache and jump into
__text_start.
JIRA IDs placed in comments for missing items.
Change-Id: I3c6b8ed65e8fcf6b6a735b80cf007d0180599230
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Now matches kernel/nanokernel/include/nano_internal.h.
Change-Id: I4dbbf50aa05c55de42100a6896fe0fa3b26955ec
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ZEP-252 will handle implementation of the code here.
Change-Id: I3e9a6c7cdf2d5a3b0240317b772628fead528095
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
At the moment this just jumps into prep_c, with comments left
on other things that need to be done. Having this here ensures that
the early boot code isn't discarded by gc-sections.
vector_table.c removed, it isn't the right approach for this CPU.
Proper method for initializing reset and exception vectors still
being investigated.
Change-Id: Id7965c671f1a55c42ecfb65119497405a646bec4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.
This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.
Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Andrew Boie