Commit Graph

4 Commits

Author SHA1 Message Date
Alex Porosanu bfcfac8bf3 doc: riscv: rv32m1_vega: add BLE software link layer info
Since the experimental BLE software link layer is enabled on
the VEGABoard, add some information about it, as well as the
limitations.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
2019-11-08 15:38:57 +01:00
Peter Bigot 8e55968aba doc: correct path to boards/riscv
The board area was renamed from riscv32 to riscv back in July to
accommodate riscv64 support.  Fix the remaining references in
documentation.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-11-07 12:39:08 -06:00
David B. Kinder 82d6347355 doc: fix broken file and zephyr-app refs
found some references to files (via :zephyr_file: and :zephyr-app:) that
were moved, so the links were broken

Fixes: #19660

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-10-08 15:42:32 -05:00
Nicolas Pitre 1f4b5ddd0f riscv32: rename to riscv
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-02 13:54:48 -07:00