Commit Graph

7 Commits

Author SHA1 Message Date
Sebastian Bøe 0829ddfe9a kbuild: Removed KBuild
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00
Andrew Boie d182d0c298 tests: gen_isr_table: don't set compiler opt
Instead, just set -O0 for the particular function which needs it.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:33:33 -07:00
Wayne Ren f8d061faf7 arch: arc: add nested interrupt support
* add nested interrupt support for interrupts
   + use a varibale exc_nest_count to trace nest interrupt and exception
   + regular interrupts can be nested by regular interrupts and fast
interrupts
   + fast interrupt's priority is the highest, cannot be nested
* remove the firq stack and exception stack
   + remove the coressponding kconfig option
   + all interrupts (normal and fast) and exceptions will be handled
     in the same stack (_interrupt stack)
   + the pros are, smaller memory footprint (no firq stack), simpler
     stack management, simpler codes, etc.. The cons are, possible
     10-15 instructions overhead for the case where fast irq nests
     regular irq
* add the case of ARC in test/kernel/gen_isr_table

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-10 12:47:15 -04:00
Kumar Gala eaaa175b92 tests: convert to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.

Jira: ZEP-2051

Change-Id: I6c676bc6c5e850a8725785554cd535e32067f33e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 09:53:49 -05:00
Jean-Paul Etienne 9acda0f695 tests: gen_isr_table: account for riscv32 architecture
Account for riscv32 SOCs supporting the riscv privileged architecture.

Change-Id: I8c26a2bcc2baded5db252896abe6e1b5ab052113
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-22 14:59:01 +00:00
Andrew Boie 5c335ce55f tests: gen_isr_table: actually run the IRQ
So far, only implemented on ARM.
It's not possible to do this on Nios II and RISC-V.

Change-Id: I84c8d99cd163dff46de4bc4a7ae40768daf8e4ce
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:18 +00:00
Andrew Boie 122467e9ee tests: add test for gen_isr_table
This test is intended to verify that the SW ISR and vector tables
have been populated correctly.

Change-Id: Ic7f50c02dc0807d7ddefa710da67f818ff707ad6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:28:00 +00:00