Commit Graph

47987 Commits

Author SHA1 Message Date
Jedrzej Ciupis 91e0895e9a west.yml: Update hal_nordic revision
Update hal_nordic to bring build warning fix for 802.15.4 serialization.

Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
2021-01-25 14:26:53 +01:00
Vinayak Kariappa Chettimada c2513eb993 Bluetooth: controller: Fix PHY update procedure cachability
Fix missing PHY update procedure cachability omitted in
commit 16dbb9a4fe ("Bluetooth: controller: split: Fix cmd
disallowed and collision disconnects").

Relates to #31473.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2021-01-25 11:49:28 +01:00
Henrik Brix Andersen 7b9b3cfe5a samples: canbus: canopen: mass-erase flash prior to running sample
Mass-erase the flash prior to running the sample to ensure the storage
partition can be initialized correctly.

Fixes: #30477

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-01-24 21:22:25 -05:00
Anas Nashif ef1b4d45b0 release: Zephyr 2.5.0-rc1
Set version to 2.5.0-rc1

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-24 17:15:54 -05:00
Matija Tudan 1463596205 drivers: dac: added driver for TI DACx3608
The DAC53608 and DAC43608 (DACx3608) are lowpower, eight-channel,
voltage-output, 10-bit or 8-bit digital-to-analog converters (DACs)
respectively. They support I2C with a wide power supply range
from 1.8 V to 5.5 V, and a full scale output voltage range of
1.8 V to 5.5 V. The DACx3608 also includes per channel, user
programmable, power down registers.

Signed-off-by: Matija Tudan <mtudan@mobilisis.hr>
2021-01-24 14:28:05 -05:00
Klaus H. Sorensen 4e7b5769bd lib: crc32_sw: 4 bit at a time implementation
Calculate crc32 4 bits at a time. The return value of the calculation is
identical to the previous 1 bit at a time implementation.

Results in a speed up of a factor 3 at the cost of using 64 bytes of
flash for a crc table.

Calculating crc32 of 128kB of flash on a 120MHz Kinetis MKE16F512
Cortex-M4 takes 99ms using the 1 bit at a time implementation, and 30ms
using the 4 bits at a time implementation.

The crc32 routine is used by subsys/canbus/canopen/canopen_program.c to
calculate crc of flash images.

Signed-off-by: Klaus H. Sorensen <khso@vestas.com>
2021-01-24 14:24:48 -05:00
Enjia Mai e89fe33a5a tests: thread: refine the thread abort test case
Refine the thread abort test case and add one extra condition.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-01-24 14:18:00 -05:00
Jian Kang 30bf585e10 tests: kernel: Add some testcases for thread
Add some error condition of testcases to verify whether the
robustness of API. Such as give a NULL to some API and check
the response if get result that we were expacted.

Signed-off-by: Jian Kang <jianx.kang@intel.com>
2021-01-24 14:13:29 -05:00
Volodymyr Babchuk b07065d3f3 arm: aarch64: add Xen virtual machine support
This commit adds minimal support for running zephyr as Xen guest. It
does not use xen PV console, which is somewhat hard to implement, as it
depends on xenbus infrastructure. Instead SBSA-compatible PL011 uart is
used.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
2021-01-24 13:59:55 -05:00
Volodymyr Babchuk 4fb1ee771a drivers: pl011: add SBSA mode
ARM Server Base System Architecture defines Generic UART interface,
which is subset of PL011 UART.

Minimal SBSA UART implementation does not define UART hardware
configuration registers. Basically, only FIFOs and interrupt management
operation are defined.

Add SBSA mode to PL011 UART driver, so it can be used at SBSA-compatible
platforms, like Xen guest.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
2021-01-24 13:59:55 -05:00
Volodymyr Babchuk 490408fa8e aarch64: introduce explicit instructions to access MMIO
With classic volatile pointer access gcc something generates
access instructions with immediate offset value, like

str     w4, [x1], #4

Such instructions produce invalid syndrome in HSR register when are
trapped by hypervisor. This leads to inability to emulate device access
in hypervisor.

So we need to make sure that any access to device memory is done
with plain str/ldr instructions without offset.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
2021-01-24 13:59:55 -05:00
Volodymyr Babchuk cd86ec2655 aarch64: add ability to generate image header
Image header is compatible with Linux aarch64 boot protocol,
so zephyr can be booted with U-boot or Xen loader.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
2021-01-24 13:59:55 -05:00
Yonatan Schachter 7191b64c6f gen_isr_tables: Added check of the IRQ num before accessing the vt
At its current state, the script tries to access the vector table
list without checking first that the index is valid. This can
cause the script to crash without a descriptive message.
The index can be invalid if an IRQ number that is larger than
the maximum number allowed by the SOC is used.
This PR adds a check of that index, that exits with an error
message if the index is invalid.

Fixes #29809

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2021-01-24 10:12:54 -05:00
Martin Åberg b6b6d39bb6 lib/os/heap: introduce option to force big heap mode
This option allows forcing big heap mode. Useful on for getting 8-byte
aligned blocks on 32-bit machines.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-24 10:11:11 -05:00
Martin Åberg 80b9080f9d tests/mem_alloc: check that malloc() objects can be accessed
Adds tests checking that we can use memory allocated by malloc(),
calloc() and realloc() to access objects of some common types,
including uint64_t and double.

It works by doing a number of allocations of various sizes and
dereferencing the returned pointer. The purpose is to catch cases where
the application would trap if accessing the allocated memory. (The
test does not check alignment against the ABI or alignof().)

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-24 10:11:11 -05:00
Martin Åberg 180ce491ad libc/minimal: reallocarray() in terms of realloc()
reallocarray() is defined in terms of realloc(). From OpenBSD manual
pages:
    "Designed for safe allocation of arrays, the reallocarray()
    function is similar to realloc() except it operates on nmemb
    members of size size and checks for integer overflow in the
    calculation nmemb * size."

The return value of sys_heap_realloc() is not compatible with that
of realloc().

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-24 10:11:11 -05:00
Kari Hulkko 22c0d0155a usb: fix for parallel transfer deadlock with usb_transfer_sync()
Parallel transfer to same endpoint is not supported and
may cause a deadlock. Adding a check to prevent starting
the transfer if tranfer is already ongoing on same endpoint.

Transfer status was not checked when accessing to transfer
from endpoint callback. Adding status check, to prevent
a double completion.

Fixes #30736

Signed-off-by: Kari Hulkko <kari.m.hulkko@gmail.com>
2021-01-24 10:08:27 -05:00
Andrew Boie 77861037d9 x86: map all RAM if ACPI
ACPI tables can lurk anywhere. Map all memory so they can be
read.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie c56b41f9b3 boards: x86: increase VM size on PC-like
These are all PC systems which have large amounts of memory
which needs to be mapped at runtime (most are 2GB).

Increase the address space size accordingly, adding an extra
8MB for mappings.

The ACRN target has 8MB, give it 16MB of VM.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 14c5d1f1f7 kernel: add CONFIG_ARCH_MAPS_ALL_RAM
Some arches like x86 need all memory mapped so that they can
fetch information placed arbitrarily by firmware, like ACPI
tables.

Ensure that if this is the case, the kernel won't accidentally
clobber it by thinking the relevant virtual memory is unused.
Otherwise this has no effect on page frame management.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 6c97ab3167 mmu: promote public APIs
These are application facing and are prefixed with k_.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 79d73063af tests: context: disable if DEMAND_PAGING
Until #31333 is resolved, the periodic timer in the eviction
algorithm interacts with this test in such a way that the system
deadlocks.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie c7be5dddda mmu: backing stores reserve page fault room
If we evict enough pages to completely fill the backing store,
through APIs like k_mem_map(), z_page_frame_evict(), or
z_mem_page_out(), this will produce a crash the next time we
try to handle a page fault.

The backing store now always reserves a free storage location
for actual page faults.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie cad944e259 tests: demand_paging: add more API tests
Add remaining APIs in mem_manage.h even though not all have
been promoted to public (yet).

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 60d306642e kernel: add z_num_pagefaults_get()
Simple counter of number of successfully handled page faults by
the core kernel.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 9a12d6028b CODEOWNERS: add demand paging subdir
Adding myself as original author.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie ef65597b73 tests: add intial demand paging testcase
More to be added, but for now show that we can map more
anonymous memory than we physically have, and that reading/
writing to it works as expected.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 146eaf4335 tests: add basic k_mem_map() test
Show we can measure free memory properly and map a page of
anonymous memory, which has been zeroed and is writable.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 611b626b39 mmu: pin the whole kernel
This will enable testing of the implementation until the
critical set of pages is identified and known to the
kernel.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 4d6c20b9d7 qemu_x86_tiny: enable demand paging
This target is specifically for simulating x86 micro-
controllers with limited memory.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie ed22064e27 x86: implement demand paging APIs
All arch_ APIs and macros are implemented, and the page fault
handling code will call into the core kernel.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie b0d608e3c9 demand_paging: add RAM-based demo backing store
Will be used by QEMU targets for testing purposes.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 367cfa4946 demand_paging: add NRU algorithm
Simple textbook Not Recently Used eviction algorithm.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie d50b2419b8 tests: mem_map: pin test pages
These get mapped to multiple virtual addresses and must be
pinned.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie a5cb878144 kernel: add demand paging implementation
Implement runtime APIs for pinning, paging in, and evicting
memory, as well as the page fault hook called from architecture
code.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie b9bbef2a2c kernel: add app-facing demand paging APIs
Routines to evict memory, page-in memory, and set pinned state
at runtime.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 431b7c0fe5 kernel: add demand paging internal interfaces
APIs used by backing store and eviction algorithms.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 993cf9f8eb demand_paging: add infra for demand paging modules
Backing stores and eviction algorithms will be included here.
Exactly one must be chosen, with a default option to leave
the implementation to the application.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie a6eca9fab6 kernel: add demand paging arch interfaces
Architecture layer hooks for demand paging. See
doxygen for these API definitions for more details.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 56a9e7b91e arch: add CONFIG_DEMAND_PAGING
Indicates at the kernel level that demand paging is active.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie ecb25fec51 mmu: ensure gperf data is mapped
Page tables created at build time may not include the
gperf data at the very end of RAM. Ensure this is mapped
properly at runtime to work around this.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 299a2cf62e mmu: arch_mem_map() may no longer fail
Pre-allocation of paging structures is now required, such that
no allocations are ever needed when mapping memory.

Instantiation of new memory domains may still require allocations
unless a common page table is used.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie b0b7756756 x86: pre-allocate address space
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.

We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.

The default address space size is now 8MB, but this can be
tuned by the application.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie ea10c98c08 qemu_x86_tiny: don't use first megabyte at all
Just tell the kernel that RAM starts 1MB in, period.
Better simulation of a low-memory microcontroller as
we're not managing a very large number of page frames
we'll never use.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 5c47bbc501 x86: only map the kernel image
The policy is changed and we no longer map all page frames.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie e2b62b8abb newlib: clamp max heap size on MMU systems
Previously, newlib claimed all free physical memory in the
system.

Now, the kernel manages this, allowing for memory to be
used via k_mem_map() calls.

Establish an upper bound to how much newlib will try to
claim on system startup, instead of trying to take all
of it, allowing other parts of the system to also map
anonymous memory.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie b01177156f newlib: memory-map the heap, cleanups
We now draw heap memory from an anonymous memory mapping
instead of a hard-coded region past the kernel image,
which is no longer mapped by default.

Some readability cleanups were made to a particuarly
horrible set of nested ifdefs. A few types were adjusted.

sbrk()'s count argument is an intptr_t, not an int.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 893822fbda arch: remove KERNEL_RAM_SIZE
We don't map all RAM at boot any more, just the kernel image.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 61651976c2 x86: tests: pagetables: fix assumptions
All RAM may not be mapped. Check the mapping for the main kernel
image and the locore if it exists.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie f3e9b61a91 x86: reserve the first megabyte
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00