Commit Graph

693 Commits

Author SHA1 Message Date
Mahesh Mahadevan d13ffceb62 timer: nxp: Update OS-Timer to use wakeup-source flag
Enable the OS Timer to be a wakeup source only if
configured through device tree property.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-10-27 11:03:13 +02:00
Kumar Gala fc95ec98dd smp: Convert #if to use CONFIG_MP_MAX_NUM_CPUS
Convert CONFIG_MP_NUM_CPUS to CONFIG_MP_MAX_NUM_CPUS as we work on
phasing out CONFIG_MP_NUM_CPUS.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-10-20 22:04:10 +09:00
Tom Burdick 94251ac843 timer: APIC timer count is a lock free accessor
Selects the hidden Kconfig to note that the APIC timer's cycle count
accessor is a lock free path and may use the spin lock time limit check.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-10-18 14:14:12 +02:00
Tom Burdick 6277386591 timer: cAVS cycle count is lock free
Select the Kconfig option noting that the cavs (intel adsp)
timer driver provides a lock free cycle count accessor and
therefore can be used with a spin lock time limit assert.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-10-18 14:14:12 +02:00
Tom Burdick 872e3553f9 kernel: Option to assert on spin lock time
Spin locks held for any lengthy duration prevent interrupts and
in a real time system where interrupts drive tasks this can be
problematic. Add an option to assert if a spin lock is held for
a duration longer than the configurable number of microseconds.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-10-18 14:14:12 +02:00
Gerard Marull-Paretas 178bdc4afc include: add missing zephyr/irq.h include
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-17 22:57:39 +09:00
Enjia Mai dcda15d17d drivers: timer: use sys_read64 to read HPET counter on 64 bits cpu
For 32 bit processor to read the 64 bits hpet counter, the HPET spec
2.4.7 suggest to read HPET counter high and low then checking the
high bits to decide if it rollovers or not.

But this logic seems to cause problem for 64 bits processor under SMP,
there is a possible one tick earier under tickless mode. It is likely
to be the cache coherence issue, because a mfence instruction before
reading the timer works.

So we change to read the 64 bits counter by sys_read64 on 64bit
processor to prevent this issue.

Fixes #49611

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-10-12 18:47:19 +09:00
Anas Nashif ede94516b0 drivers: intc_dw_ace: rename file
No need for the version in the file name, this will be used by multiple
versions of ACE.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 12:50:05 -04:00
Anas Nashif 0869e62539 intel_adsp: cleanup ace_v1x-regs.h more and prep for removal
File still not being removed due to out-of-tree usage. We will drop it
once the external code has stopped referencing it.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 12:50:05 -04:00
Anas Nashif 52297422fc timer: intel_adsp: use DTS for hardware information
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 12:50:05 -04:00
Anas Nashif 059dc41cc6 intel_adsp: put interrupt defines in own headers/cleanup namespace
Cleanup soc.h and move interrupt defines into own headers. Rename some
of the defines for ACE to have a unified namespace.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 12:50:05 -04:00
Anas Nashif 100090832d drivers: intc: ace: use DW structure already defined in the driver
The DW register block was duplicated into the ACE header while we had
the same thing in the driver. Move everything to the driver as the first
step with further improvements planned on top of this.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 12:50:05 -04:00
Gerard Marull-Paretas ac63bca423 include: add missing sys_clock.h include
Some headers made use of types defined in sys_clock.h (e.g. k_timeout_t)
without including it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Gerard Marull-Paretas 357b362824 include: add missing sys/time_units.h include
Some files using time_units.h API did not include it, e.g. for
sys_clock_hw_cycles_per_sec.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Gerard Marull-Paretas 597dd5901c include: add missing spinlock.h include
Some files are using the spinlock API without including the necessary
headers.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Gerard Marull-Paretas 4ba74c2ec9 include: add missing limits.h include
Some files used definitions found in limits.h (e.g. INT_MAX) without
including it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Gerard Marull-Paretas 6a0f554ffa include: add missing kernel.h include
Some files make use of Kernel APIs without including kernel.h, fix this
problem.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Gerard Marull-Paretas acc8cb4bc8 include: add missing irq.h include
Some modules use the IRQ API without including the necessary headers.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Gerard Marull-Paretas 34a6848887 include: add missing arch/cpu.h include
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Peter Mitsis d308ca5695 drivers: timer: adsp: Improve elapsed ticks calculations
It is better to use 64-bit variable types for calculating the number
of elapsed ticks than 32-bit variable types. This guards against the
propagation of calculation errors should the lower 32-bits of the timer
counter roll over multiple times before the timer ISR is serviced.

(Such a scenario can easily occur when pausing the system for an
extended period of time with a debugging device such as a Lauterbach.)

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2022-10-07 18:34:50 -04:00
Erwan Gouriou 2d740d42e0 drivers: timer: stm32_lptim: Change clock source config check sanction
A specific check is implemented lptim driver in order to ensure global
platform clock/tick configuration is in line with recommendations.
To respect portability principles, don't error out when a config
conflict is detected but generates a warning instead.
Also, since these are only recommendations, provide an option to override
the check. Besides automatically override when ZTEST is enabled, as some
kernel tests specifically configure tick freq to 100.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-21 18:39:07 +00:00
Flavio Ceolin 45465708f0 soc: intel_adsp: Add ACE soc series
ACE15_MTPM is one SOC from the ACE series. Organize
it following cavs pattern.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:03:59 -04:00
Erwan Gouriou d62450886b drivers: timer: stm32_lptim: Initialize static global variable
In some configurations, a udf instruction may be generated
when compiling code where static global variable lptim_clock_freq is
used as a divisor.
To avoid this, initialize variable on declaration so that compiler
could see that it can't be used uninitialized in this division.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-09 14:09:22 +00:00
Kumar Gala cc2c05a90c drivers: timer: Update drivers to use devicetree Kconfig symbol
Update timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.

We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-09 09:58:48 +00:00
Erwan Gouriou ec6f932ad2 drivers/timer: stm32 lptim: Fix frequency check
Aim is to error out on misconfifurations, not the other way round.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-07 15:39:16 +02:00
Gerard Marull-Paretas 79e6b0e0f6 includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.

The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.

NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-09-05 16:31:47 +02:00
Erwan Gouriou e8e72882e1 drivers: timer: stm32: Check return of clock functions
That will speed up debugging.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-02 10:41:59 +00:00
Erwan Gouriou 7f2cb0fd22 drivers: timer: stm32: Specific handling for L0 LSI
On L0 series, LSI runs at 37KHz while LPTIM driver only supports speeds
up to 32768Hz (to avoid counter overflow). Consequence is a time running
faster than reality (x1.13)
Solution to this is the implementation of the LPTIM prescaler support.

While moving driver configuration from Kconfig to DT, this case was
not taken into account and the effect was LPTIM counter overflow which
consequence is worse than the slightly faster timer.
Reproduce the initial behavior with this piece of code that will be
removed once prescaler support is available.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-02 10:41:59 +00:00
Erwan Gouriou 16c11138d5 drivers: timer: stm32: Adapt SYS_CLOCK_TICKS_PER_SEC
When using LPTIM as tick source, tick freq (SYS_CLOCK_TICKS_PER_SEC)
needs to be adapted to get a precise tick to LPTIM freq ratio.

This adaptation was done easily using Kconfig up to now (under
soc/st_stm32/common/Kconfig.defconfig.series).
Since driver is configured using device tree, this method should
be adapted. For the LSI case (default Kconfig case), rely on the
existing mecanism, which is also still used by OOT users.
For the LSE case, force the value manually in boards forlder.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-02 10:41:59 +00:00
Erwan Gouriou d056be2b38 drivers/timer: stm32: Re-instantiate warning message on lptim configuration
Following transition of lptim timer configuration from Kconfig to DT,
a warning message was set to inform users about this deprecation.
Due to errors in CI this message had to be removed while fixing the related
issues.
Now these issues are fixed, set the deprecation message again.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-02 10:41:59 +00:00
Erwan Gouriou f818b0478d drivers/timer: stm32: Enable lptim driver based on dt status
Similarly to other drivers, use auto generated DT_HAS_<COMPAT> Kconfig
symbol to control use of STM32 lptim driver.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-02 10:41:59 +00:00
Sylvio Alves 7a00f7b793 west.yml: update hal to v4.4.1 base
west.yml: update hal_espressif to use latest v4.4.1 updates.
This change needs to be insync with esp32c3 timer changes, otherwise it
breaks it.

drivers: timer: update esp32c3 systimer to meet API changes.
Systimer API was refactored in hal v4.4.1, which
requires updates in esp32C3 systimer. Timer behavior is maintained
as is.

mcpwm: add v4.4.1 include reference, which was refactored as well.

driver: spi: esp32: update internal structs to meet API changes.

cmake: updated esp32 board to use HAL_ prefix as from west blobs
requirement.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-09-01 21:48:18 +00:00
Adam Zelik d0bb17ab37 drivers: timer: Increase default user-allocable channel count to 3
Increase the default user-allocable number of RTC channels to meet
the nrf_802154 driver requirements.

Signed-off-by: Adam Zelik <adam.zelik@nordicsemi.no>
2022-08-19 12:08:59 +02:00
Gerard Marull-Paretas e0125d04af devices: constify statically initialized device pointers
It is frequent to find variable definitions like this:

```c
static const struct device *dev = DEVICE_DT_GET(...)
```

That is, module level variables that are statically initialized with a
device reference. Such value is, in most cases, never changed meaning
the variable can also be declared as const (immutable). This patch
constifies all such cases.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-19 11:51:26 +02:00
Erwan Gouriou f2b3be172b drivers: timer: lptim: Remove deprecation warning
It appears that some in tree boards still enable lptim w/o configured
domain clocks.
Remove this deprecation message the time a clean up is done fully.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-08-12 14:25:51 -05:00
Erwan Gouriou bbac316be7 drivers: timer: stm32: Use dt to configure LPTIM domain clock
Instead of relying on Kconfig, use dt inputs to configure LPTIM domain
clck (LSI/lSE).
Clock control dedicated APIs are used for configuration and get the
frequency of domain clock in use.
Constants macros used previously to store frequency and time base are
converted to static global variables.

Some code was set up specifically to keep compatibility with targets
that still use Kconfig to configure domain clock. This will be removed
after a deprecation period.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-08-12 08:50:29 +01:00
Erwan Gouriou 7f6d3e5336 drivers: timer: stm32: Use dt instance for LPTIM bus clock
Continue conversion of LPTIM driver to device tree based configuration.
Get clock configuration from device tree and use clock_control API for
bus clock configuration

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-08-12 08:50:29 +01:00
Erwan Gouriou f8b1a18271 drivers: timer: stm32: Use dt instance for LPTIM base address /IRQ
Start converting LPTIM driver to device tree based configuration and
support of other instances.
First: get base address and IRQ using dt instance

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-08-12 08:50:29 +01:00
TOKITA Hiroshi eca3b1067e dts: riscv: gd32vf103: Use IRQ7 for interrupt of riscv_machine_timer
IRQ7 is placed on the second element of interrupt definition.
Select it by DT_INST_IRQ_BY_IDX() explicitly.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-08-10 13:08:27 +02:00
Henrik Brix Andersen e9f4c91a02 drivers: timer: check if clock device is ready before accessing
Add check for device_is_ready() before accessing clock control devices.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-08-09 17:16:16 +02:00
Julien D'Ascenzio a703cbe9ce drivers: timer: stm32 lptim fix long time interrupt locking
The waiting of the flag ARROK could be quite long (100µs-200µs in my
test). During this time, the interrupts are locked that is not
recommended. To avoid this, we manage the update of the autoreload value
in interruption

Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
2022-08-09 12:31:28 +02:00
Stephanos Ioannidis 4004475e7f drivers: timer: nrf_rtc_timer: Fix assert conditions
This commit fixes the incomplete assert conditions for the `chan`
argument passed to the nRF RTC timer functions.

Note that the `chan` argument for this driver is of a **signed**
integer type, so it is necessary to check that its value is
non-negative.

This fixes the warnings generated by the GCC 12 such as:

  error: array subscript -1 is below array bounds of '...'

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-08-05 15:15:34 +02:00
Gerard Marull-Paretas 149fe06341 drivers: arc/designware: remove unused <soc.h>
The <soc.h> header is not required by a few ARC/Designware drivers, so
remove it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Gerard Marull-Paretas 5f40a9f40f soc: arc: synopsys: move secure timer0 definition to DT
Use Devicetree to describe secure timer0 instead of hardcoding values in
<soc.h>.

DT files have been structured to match the following requirements: In
case of sectimer0 - it's should be only enabled for:

- emsdp_em7d_esp.dts
- em_starterkit_em7d.dts
- nsim_sem_mpu_stack_guard.dts
- nsim_sem.dts

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Gerard Marull-Paretas 44250fe3d3 soc: arch: synopsys: move timer0/1 IRQ information to DT
timer0/1 IRQ information was hardcoded in soc.h, however, Devicetree is
nowadays a better place to describe hardware. Note that I have followed
existing upstream Linux code to do these changes.

Ref.
- https://elixir.bootlin.com/linux/latest/source/arch/arc/boot/dts/
  hsdk.dts
- https://elixir.bootlin.com/linux/latest/source/Documentation/
  devicetree/bindings/timer/snps,arc-timer.txt

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Gerard Marull-Paretas 732c00e29a drivers: timer: riscv_machine_timer: fix compatible comment
The andestech,machine-timer comment was incorrectly set to
neorv32-machine-timer.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 05:03:50 +01:00
Gerard Marull-Paretas 1c41423210 drivers: timer: riscv_machine_timer: obtain registers/IRQ from DT
Obtain machine timer addresses and IRQ from Devicetree. Note that driver
supports multiple compatibles because mtime/mtimecmp registers are
implemented in different ways depending on the vendor. That means
Devicetree representations can be slightly different and so code to
collect the information needs to treat each compatible differently.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Anas Nashif 728d8eb2c0 intel_adsp: rename clock registers due to possible conflict
SOF using the same defines and in some cases generating conflicts.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-28 14:11:23 -04:00
Anas Nashif 2af59e7d44 intel_adsp: unify timer registers and simplify timer driver
Declare clock control in the shim header per SoC and remove ifdeffry
from the driver simplifiying it and making it ready for the next
platform.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif 423264b96b intel_adsp: make shim header soc specific
using once single header to support multiple socs and product
generations is error prone and not easily maintained.

Over time we have been adding conditional code in headers and extending
structs  to support new HW features which becomes a problem.

Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.

This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00