Commit Graph

17 Commits

Author SHA1 Message Date
Gil Pitney 4f67a6c76d cc3200: Remove TI cc3200 SOC and LaunchXL board support
Per ZEP-1958, Phase 2 of adding CC3220sf LaunchXL support,
was to "deprecate the CC3200 launchxl support in Zephyr
(redundant to the CC3220)."

Effectively, the CC3220 SOC replaces the CC3200.

This patch removes the following:
* the imported CC3200 SDK
* CC3200 SOC, board, DTS files.
* adjusts other files where cc3200 was mentioned.

Also, it fixes explicit references to CC3200 in generic
CC32xx driver files.

Jira: ZEP-1958

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-08-15 11:02:48 -05:00
Yannis Damigos 1a652e3ef1 dts: Remove memory node from skeleton dtsi file
Remove memory node from skeleton dtsi and add device_type
property in every memory node in soc dtsi files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-07-21 12:20:49 -05:00
Yannis Damigos 399a6bec0f dts: arm: Add unit-address component to memory and flash nodes
This patch add the unit-address component to memory and flash
nodes. According to the DT specification, the unit-address of
a node must match the first address specified in the reg
property of the node.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-07-21 12:20:49 -05:00
Kumar Gala 4cace27c82 dts: cleanup usage of "flash" and "sram" compatible
Remove compatible = "flash" from any node that has it as this doesn't
have any well defined meaning right now.  Also update any compatible =
"sram" to be "mmio-sram" (as there's a binding in linux for this).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-20 09:56:41 -05:00
Yannis Damigos 941ffb017b dts: Add cpus and cpu nodes missing properties
This patch adds #address-cell, #size-cell properties to
cpus container node and device_type, reg properties to
cpu node.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-07-19 14:28:08 -05:00
Geoffrey Le Gourriérec 0abeba8b1a sensortag: Add TI's SensorTag board.
Add support for TI's SensorTag board, which uses a CC2650 SoC.

Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
2017-06-16 16:18:12 -04:00
Geoffrey Le Gourriérec fdf1785775 arm: Add support for TI's CC2650 SoC.
Add support in arch/arm/soc/ti_simplelink, along with support
for CC32xx SoC.

Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
2017-06-16 16:18:12 -04:00
Anas Nashif 3405607d9e license: add missing licenses and copyright
We were missing license boilerplate in many files, add them

Jira: ZEP-1464

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-08 10:41:56 -04:00
Kumar Gala 22874ef301 arm: ti: stellaris: dts: use label to generate TI Stellaris uart name
Now that we can utilize label in the device tree we can convert to
getting the device name for the TI Stellaris UART out of the device
tree instead of from Kconfig.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-05-19 10:06:48 -04:00
Kumar Gala f13af29741 arm: ti: cc32xx: dts: use label to generate TI CC32xx uart name
Now that we can utilize label in the device tree we can convert to
getting the device name for the TI CC32xx UART out of the device
tree instead of from Kconfig.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-05-19 10:06:48 -04:00
Kumar Gala ac0bb050dd arm: dts: ti_lm3s6965: Add device tree support for Stellaris UART
Converted Stellaris UART driver over to utilize device tree generated
defines.  Added a yaml description for the uart, and converted over the
ti_lm3s6965 SoC & qemu_cortex_m3 board port over to utilize it.

Change-Id: Ie20844eb63d2c68eb59ad4160f7f5b5a35e2943b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:40 -05:00
Kumar Gala f6284cfbec arm: dts: ti_lm3s6965: Add Device Tree Support
Introduce a simple device tree for the TI lm3s6965 SoC and QEMU
Cortex-M3 board port.  We get flash and memory base addresses and sizes
from the device tree as well as the ARM NVIC number of priority bits.

Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:40 -05:00
Kumar Gala 567b733e76 arm: ti: dts: fixup building CC3200 dts
The CC3200 doesn't have on chip flash, so we should be including it in
the dts.

Change-Id: I8d4bbe2b09ed1aa563efe4c979da1f4729b93534
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:38 -05:00
Gil Pitney 70040f0e11 boards: Add support for the CC3220SF_LAUNCHXL board
CC3220SF_LAUNCHXL effectively replaces the CC3200_LAUNCHXL,
with support for the CC3220SF SoC, which is an update for
the CC3200 SoC.

This is supported by the Texas Instruments CC3220 SDK.

Jira: ZEP-1958

Change-Id: I2484d3ee87b7f909c783597d95128f2b45db36f2
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-04-28 15:06:41 -05:00
Gil Pitney de20a6558a cc3200: Make use of mem.h file in soc dtsi file.
This in preparation for adding a cc3220sf DTS file, which
has a different address for sram0 than the cc3200.

Also moved baud-rate out of soc dtsi file to board dts.

Jira: JEP-1958

Change-Id: I641452c0a8a6d1ad4424e132d6ef2de71d8545b4
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-04-28 15:06:40 -05:00
Kumar Gala 1df7eba02c dts: arm: ti: Use hardcoded addresses in cc32xx_launchxl.dtsi
In general we should be using hardcoded addresses in the dtsi files
rather than getting ifdef from other places.  As the unit address of the
node is typically based on the address in hex w/o the '0x' we can't just
use #defines directly.

Change-Id: I0e17e001151728d16842806d9407e66e6e5129cf
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-13 15:01:57 +00:00
Kumar Gala d1821640b3 dts: arm: move SoC dtsi into per vendor dir
Move the SoC dtsi into a vendor dir so as we grow and possibly share
things with other projects we are hopefully in sync (or closer to it).

Change-Id: I71666cff49f9694eee3f5d92dac8aeea416b730a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-04 17:55:13 -05:00