This construction was causing errors with recent gccs. If you look
carefully, it's generating the sequence:
simcall
mov a2, a2
mov a3, a3
...which is nonsensical. And now gcc is complaining about it with:
subsys/logging/log_backend_xtensa_sim.c:44:2:
error: invalid hard register usage between output operands
Just emit a single simcall instruction and let the assembly
constraints do their job.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Ensure that RTT and xtensa_sim backends are using single byte
log_output buffer.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Andy Ross