Commit Graph

4 Commits

Author SHA1 Message Date
Gerard Marull-Paretas c17ee81af4 dts: riscv: microsemi-miv: define CLINT
The SoC seems to embed a CLINT instance, defined at 0x44000000.

Ref. https://github.com/Mi-V-Soft-RISC-V/platform/blob/main/
miv_rv32_hal/miv_rv32_hal.h

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Kumar Gala b385afb6fd dts: riscv: Remove label property from devicetrees
Label properties are not required.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 12:57:23 -05:00
Olof Johansson 07ac630281 dts: riscv: add #address-cells to all interrupt controllers
This mirrors #36499 and other PRs that added them for other
architectures.

This silences a large number of dtc warnings due to the missing
property. It seems reasonable to require an address-cells property since
any interrupt controller could be the parent of an interrupt-map.

The only device actually using interrupt-maps is neorv32, and it needs
an address-cells of 2 (since this is the default if none is specified it
worked like that before this change).

While I touched this, I reordered the properties for consistency across
boards, but there's a lot of variance here already.

Signed-off-by: Olof Johansson <olof@lixom.net>
2022-07-04 14:39:43 -04:00
Maureen Helm 3142b6d328 dts: riscv: microsemi: Move SoC devicetree includes under a vendor dir
Cleans up SoC devicetree include file locations to follow the convention
of dts/<arch>/<vendor>/

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-05-09 17:54:48 -04:00