Commit Graph

123 Commits

Author SHA1 Message Date
Jay Vasanth ae9de20222 drivers: spi: Added MEC172x full duplex qmspi driver
Add MEC172x full duplex qmspi driver version to support full
duplex transfers as expected by the Zephyr spi driver model.
On every spi clock we transmit one bit and receive one bit.
This driver will work with Zephyr SPI NOR driver.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-10-14 14:09:51 -05:00
Jay Vasanth 3f1da206f8 dts: microchip: spi: move common properties to a separate include
updated dts variables naming (hyphen instead of underscore).
moved all properties in microchip ldma yaml to a separate include file,
these properties will be common with the (to be added)
full duplex spi driver.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-10-14 14:09:51 -05:00
Lucas Tamborrino a11a103518 drivers: spi: esp32/s2: add DMA support
Add SPI DMA support for esp32/s2.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2022-10-04 10:35:14 +02:00
Jay Vasanth d6ba6a5fac spi: mec15xx: add pinctrl for mec15xx/mec1501 qmspi
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 qmspi. Update board dts, pinmux and driver files.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-09-21 18:05:32 +00:00
Kevin Wang 93025635b3 dts: bindings: spi: add andes spi driver
Add Andes SPI atcspi200 dts binding.
Remove not necessary property for spi node in soc dtsi.

Signed-off-by: Kevin Wang <yunkai@andestech.com>
2022-09-07 15:34:47 +02:00
Gerard Marull-Paretas 64eb350e5e drivers: spi: gd32: use clock control API
Use the clock control API to enable/get rate of SPI clocks.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-06 09:57:25 +02:00
Gerard Marull-Paretas d55bc1f7ba drivers: spi: gd32: use reset API
Use the reset API to reset the peripheral state before initialization.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-29 10:30:49 +02:00
TOKITA Hiroshi a7721aa30d drivers: spi: pl022: Support interrupt based transfer
Add interrupt based transfer feature for the PL022 SPI.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2022-08-18 10:18:16 +02:00
TOKITA Hiroshi 8a8e893bd2 dts: arm: rpi_pico: Adding spi configurations to rp2040
Add spi0 and spi1 configuration to rp2040.

spi0 and spi1 are declared as compatible with
"raspberrypi,pico-spi" and "arm,pl022".
"raspberrypi,pico-spi" is just inherited from
"arm,pl022" and "reset-device"

spi0 and spi1 declare as compatible with "raspberrypi,pico-spi"
and "arm,pl022".
"raspberrypi,pico-spi" is just inheriting "arm,pl022" and
"reset-device" for declaring the 'reset' property,
with no additional property and implementation.

Add also pinctrl macros to dt-bindings header.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2022-08-18 10:18:16 +02:00
TOKITA Hiroshi da32e26a3d drivers: spi: Add basic support for PL022
Add fundamental feature support for PL022 SPI peripheral.
This commit implements synchronous transfer with 8bit-MSB format.

Optional functions are not currently implemented yet.

- interrupt based transfer is not implemented yet.
- DMA transfer is not implemented yet.
- Slave mode is not implemented yet.
- Currently support only 8-bit data transfer.

Hardware limitation:

- LSB-first format is not supported by hardware.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2022-08-18 10:18:16 +02:00
XiNGRZ Chan 7109632046 drivers: spi_esp32_spim: Add support for IOMUX mode
In order to work on a clock speed higher than 20 MHz, IO MUX is required.

Co-authored-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Signed-off-by: XiNGRZ Chan <hi@xingrz.me>
2022-08-09 12:31:23 +02:00
Bryce Wilkins 5ff80ef2b1 drivers: spi: Add default char to mcux flexcomm spi driver
Adds optional device tree property to specify a default character
to clock out when the TX buffer pointer is NULL. If the property is
not set the existing behavior (default char of 0x00) is used.

I verified the expected behavior using an i.MX RT685 board and
logic analyzer that the def-char character is transmitted when
TX buffer pointer is NULL.

Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
2022-08-05 09:28:39 -05:00
Gerard Marull-Paretas 2cfb5012db drivers: spi: nrfx_spim: move rx delay to DT
Move the RX (MISO) delaying capability information to Devicetree. It is
done using 2 properties:

- rx-delay-supported: enabled on SPI nodes that support delaying RX.
  This property can be used by the driver to determine if this
  capability is supported or not on a given instance.
- rx-delay: the actual RX delay value

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-19 13:20:00 -07:00
Gerard Marull-Paretas 3c6649f631 drivers: spi: spi_nrfx_spi(m|s): move ORC to DT
Specify the overrun character in Devicetree. Since 0xFF is the most
common value, DT property contains such default.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-19 13:20:00 -07:00
Gerard Marull-Paretas 4ad3a96059 drivers: spi: nrfx_spim: move maximum frequency parameter to DT
Devicetree is the natural place to describe hardware, so move the
maximum frequency the SPI can work with to Devicetree instead of relying
on values from HAL.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-19 13:20:00 -07:00
Kumar Gala cbc848f328 dts: bindings: device labels are now optional
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-18 10:39:14 +00:00
Kumar Gala 9680483c3d dts: bindings: device labels are now optional
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-15 08:10:36 -05:00
Kumar Gala b200b9a9e0 dts: bindings: bus labels are now optional
All in tree device drivers on a bus use some form of DEVICE_DT_GET
so we no longer need to require label properties.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-14 09:19:35 -07:00
Gerard Marull-Paretas c2d699ec2d drivers: spi: sifive: remove CONFIG_SIFIVE_SPI_0_ROM
CONFIG_SIFIVE_SPI_0_ROM (default y) was an option to disable spi0 if
used to access SPI Flash ROM. However, its design had a problem: it
relied on instance numbers. You had to set status okay for spi0 to make
it work (incongruent with the purpose of the option itself). This patch
makes things simpler: if such SPI0 is not available, simply keep it
disabled in DT. Bindings have been updated to mention this case.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-11 17:56:55 +02:00
Erwan Gouriou ccebe683c6 dts: bindings: spi: Add a new stm32h7 spi compatible
Add a stm32h7 spi compatible.
This compatible intends to match all SPI hardware blocks that
can be compatible with the one available in stm32h7 devices,
for instance, but not limited to stm32u5 and stm32mp1.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-07-04 14:23:34 +00:00
Jose Alberto Meza b6d2f22bd4 dts: bindings: spi: Use consistent dts names for mec172x
Use consistent name for SPI HW block property so applications
using a device tree overlay work transparently.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-07-04 16:18:42 +02:00
Gerard Marull-Paretas 8b6fe35cac dts: nrf: deprecate -pin properties
-pin properties, e.g. tx-pin have been replaced by pinctrl. Mark them as
deprecated since old pin configuration schemes will be deprecated in
Zephyr 3.2.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-29 14:49:51 +00:00
Adam Wojasinski d64dc771f3 drivers: spi: spi_nrfx_spim: utilize EasyDMA property from devicetree
This commit aligns SPIM shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.

When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2022-06-05 14:27:29 +02:00
Naga Sureshkumar Relli bfbcb3973a dts: riscv: introduce Polarfire SOC QSPI interface
Add support for the Microchip Polarfire SOC QSPI interface.

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
2022-05-06 11:32:54 +02:00
Henrik Brix Andersen c83a0d5d1f drivers: spi: rv32m1: lpspi: add pinctrl support
Add pinctrl support to the OpenISA RV32M1 LPSPI SPI driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Glauber Maroto Ferreira f4c3b12ad2 dts: bindings: spi: esp32: add pinctrl properties
and removes bindings previously used by the
pinmux driver.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Vaishnav Achath ace77c71e9 drivers: CC1XX/CC26XX based boards: transition to pinctrl driver
This commit has the necessary changes to update the consumers
of pinmux driver(SPI, I2C, UART) and update the board specific
files to use the pinctrl interface.

Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
2022-04-18 18:19:46 -04:00
HaiLong Yang 2e53071006 dts: arm: introduce gd32 spi interface
Add gd32 spi initial support.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2022-03-29 10:21:15 -05:00
Daniel DeGrasse 459495aa84 drivers: memc: enable pinctrl for flexspi driver
Enable pinctrl for flexspi driver. Note that when flexspi is being using
in XIP mode, pinctrl settings are not required and will not be applied.
Pinctrl settings are only required when the flexspi device being used is
not the one used for XIP.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 15:47:54 -05:00
Gerson Fernando Budke fbddf7847d drivers: spi: Add sam0 support to pinctrl
This add support to pinctrl at Atmel sam0 spi driver. It updates all
boards with new pinctrl groups format and drop pinmux entries.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Gerson Fernando Budke 38d0659931 drivers: spi: Update sam driver to use pinctrl
This update Atmel sam spi driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Filip Kokosinski 38f38e0be8 boards: FE310-based boards: transition to pinctrl driver
This commit makes the transition from the pinmux driver to the pinctrl
driver. It also modifies UART, SPI and I2C drivers used in FE310-based
boards to use the new pinctrl API.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Daniel DeGrasse 6545a3d0fa drivers: spi: enable pinctrl for spi_mcux_lpspi
Enable pinctrl for lpspi driver

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-22 12:36:04 +01:00
Daniel DeGrasse f90c356025 drivers: spi: enable pinctrl for kinetis dspi driver
Enable pinctrl unconditionally for kinetis dspi driver

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-22 12:36:04 +01:00
Andrzej Głąbek 32b9e65e4b drivers: spi: nrfx: Add support for pinctrl
Add support for the new pinctrl API to the SPI drivers that handle
the nRF SPI, SPIM, and SPIS peripherals. Update code of the drivers
and related devicetree bindings.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-03-09 12:05:22 +01:00
Jay Vasanth 99c89ebb78 qmspi: update MEC172x qmspi module for pinctrl
Changes to qmspi module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Tomasz Bursztyka ba6e9cd682 dts: Set a default value for SPI device's duplex property
Better setting a default value there so DT_PROP() will return something
relevant whether the property is set or not.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2022-01-08 06:28:57 -05:00
Jay Vasanth fd43c725d2 drivers: spi: Add MEC172x QMSPI-LDMA driver
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2021-12-08 08:43:05 -05:00
Marc Reilly 54b6d26242 drivers: spi: add spi-bitbang driver
This adds an spi master mode driver via bitbanged gpio. Only syncronous
transfers are implemented. Clock signal timing is accomplished via busy
waits, the gpios are manipulated via the standard gpio interface; these
two factors limit the frequency at which it can operate - but here
a simple and generic implementation was chosen over performance.

The driver supports the various clock polarity and phase
configurations, and can also work with word sizes which are non
multiples of 8bits, currently up to 16 bits.

A sample program is also added demonstrating basic use of the driver
with 9bit data words.

Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
2021-12-06 07:29:45 -05:00
Bryce Wilkins 219bf88fe8 drivers: spi: Add optional delays to mcux flexcomm spi driver
Adds optional device tree properties to insert delays between spi chip
select assert/deassert and the clock edges, and also between spi
frames and transfers to the mcux flexcomm spi driver. If the properties
are not set, no additional delay is inserted.

Verified expected behavior on mimxrt685_evk and check with a scope
that the pre- and post-delay could be changed from the device tree
properties.

Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
2021-12-03 16:42:10 -06:00
Tomasz Bursztyka 1c1a2ccdbd dts/bindings: Add a dedicated frame format property on SPI device
Most of the time SPI devices use TI's frame format. But some may use
Motorola's. This is already taken care of in the SPI API and now it will
be possible to select the right format from DTS. Like:

    ...
    frame-format = <SPI_FRAME_FORMAT_MOTOROLA>;
    ...

This is only meant to be used for devices supporting both formats (so
the format is not hard-coded in the driver) and selected by hardware
configuration or else.  Which, in such case, it will need to use
DT_INST_PROP(<instance number>, frame-format) macro call to retrieve
the property value. Others can fully ignore it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-29 17:17:36 +01:00
Erwan Gouriou 37bf7cbe4f dts/bindings: stm32: Set pinctrl-[0/names] properties as required
Now that STM32 drivers are using pinctrl API, set pintrl-0 and
pintrl-names properties as required in order to report malformed
nodes description soon at build stage and avoid cryptic
DT api build error messages.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou 8bd410a589 drivers/spi: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Tomasz Bursztyka 4bd5935302 dts/bindings: Add a dedicated property for duplex mode on SPI device
Users will have to include dt-bindings/spi/spi.h in order to use the
relevant flags fol this property. For instance:

    ...
    duplex = <SPI_HALF_DUPLEX>;
    ....

By default all SPI device are configured to be full duplex so the
property is optional. This property makes sense only for devices that
can be configured on either modes. Which, in such case, it will need to
use DT_INST_PROP(<instance number>, duplex) macro call to retrieve the
property value. Others can fully ignore it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-19 11:50:38 +01:00
Nick Ward fa94be591d drivers: spi_nrfx_spim: workaround for nRF52832 errata anomaly 58
See:
https://infocenter.nordicsemi.com/index.jsp?topic=%2Fstruct_nrf52%2Fstruct%2Fnrf52832_errata.html
https://infocenter.nordicsemi.com/pdf/nRF52832_Rev_3_Errata_v1.0.pdf

Code derived from the example PAN 58 workaround code.

Adds a new nRF SPIM Devicetree binding property called
anomaly-58-workaround that allows the workaround to be enabled
if required per SPIM instance.

Signed-off-by: Nick Ward <nick.ward@setec.com.au>
2021-11-09 20:04:45 -05:00
Jun Lin 5d72417df4 drivers: spi: npcx: add SPI support to access the SPI flash
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface
to access the SPI flash. This commit adds the driver support for it.
With this commit, the application can call the flash APIs
(via spi_nor.c) to access the internal flash of NPCX EC chips.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
2021-11-01 21:48:20 -04:00
Martí Bolívar f259790bf8 dts: bindings: fix file names
Make sure binding file names match their compatibles.

Done with a script.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-10-20 07:33:04 -04:00
Glauber Maroto Ferreira 26131ba5d4 esp32: drivers: spi: driver refactoring
in preparation to support other esp32-family socs

on top of existing driver.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-10-10 14:52:41 -04:00
Christopher Friedt 137594c666 Revert "dts: stm32 spi can configure the frame-format"
This reverts commit 394996313a.

Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
2021-09-30 16:04:37 -04:00
Francois Ramu 394996313a dts: stm32 spi can configure the frame-format
If supported by the SPI instance and soc, this property will
configure the frame-format to be compliant with the TI mode.
By default, if supported, the frame-format is Motorola mode.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-09-29 14:47:31 -04:00