zephyr

Commit Graph

Author	SHA1	Message	Date
Anas Nashif	d7bc60f096	kernel: remove remaining microkernel references Change-Id: Ie648dbaaf714316c21395bd43e555618013dbd19 Signed-off-by: Anas Nashif <anas.nashif@intel.com>	2017-04-10 20:21:05 +00:00
Jean-Paul Etienne	4ae030c7b8	riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>	2017-04-02 15:15:07 +00:00

Author

SHA1

Message

Date

Anas Nashif

d7bc60f096

kernel: remove remaining microkernel references

Change-Id: Ie648dbaaf714316c21395bd43e555618013dbd19
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

2017-04-10 20:21:05 +00:00

Jean-Paul Etienne

4ae030c7b8

riscv32: added support for the SiFive Freedom E310 SOC

The SiFive Freedom E310 SOC follows the riscv privilege
architecture specification and hence is declared within
the riscv privilege SOC family.

It also provides support for a riscv
Platform Level Interrupt Controller (PLIC)

Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>

2017-04-02 15:15:07 +00:00

2 Commits