An area of flash memory on the RA4M1 MCU is used to store information
used to configure the device following a reset. This patch instructs
the linker to reserve this memory area and provides kconfig options
that are used to populate it (at build time) with the desired device
configuration.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel cAVS 2.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
For CPP application, such as samples/cpp/cpp_synchronization/, it will
report the following building errors:
...
zephyrproject/modules/hal/nxp/imx/devices/MCIMX7D/./MCIMX7D_M4.h:5101:51:
error: 'reinterpret_cast<CCM_Type*>(808976384)' is not a constant
expression
...
The error is caused by commit: 72312feead
" arch: arm: cortex_m: Use cmsis api instead of inline asm in arch_irq_*"
This patch will cause kernel.h includes cmsis_core.h which includes soc.h,
so that soc.h will be used by c++ code.
This patch make soc.h can be c++ compatible.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Adds configuration that allows nRF53 and nRF91-based boards to be
flashed through west using sysbuild for multiple images with the
recover or erase options and prevent running those commands for
each image being flash, which would make the device unbootable.
Also defers reset whilst all images for the cores of these SoCs
are flashed.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The pinctrl driver actually uses SYSCON, so 'depends on' should be used
instead of 'select'. SYSCON should be selected in SoC config instead,
just like other SoC do.
This breaks Kconfig dependency loop for configs that indirectly depends
on SYSCON and causes PINCTRL to be selected.
Signed-off-by: Patryk Duda <patrykd@google.com>
This commit implement the UART asynchronous API mode support.
When the API is used, the UART hardware cooperates with the DMA (MDMA)
module to handle the the data transfer and receiving.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Using the SOC_IT8XXX2_REG_SET_V2 instead of constantly adding new
variants of the IT82XX2 SoC.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This adds automatic GPIO latching before going to extended sleep and
restoring state after wakeup.
Mode and state for each pin is stored, then ports are latched to retain
state when PD_COM is disabled during sleep. On wakeup mode and state for
each pin is restored and ports are unlatched to make it work again.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This enables cache retainability while in sleep so there's no penalty
when executing from QSPI after wakeup.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
This enabled extended sleep for Renesas SmartBond(tm).
Extended sleep is low power mode where ARM core is powered off and can
be woken up by PDC. This is default sleep mode when CONFIG_PM is
enabled.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This adds timer driver for Renesas SmartBond(tm) family.
It uses TIMER2 block which is in PD_TIM power domain so it can work even
if ARM core is disabled, thus can work as a sleep timer.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Remove CONFIG_NRF_ENABLE_ICACHE as it is not needed. There is CONFIG_ICACHE
which is by default enabled for nrf54h.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The AM64x and AM62x are both SOCs from the TI K3 family
and share common architecture designs. The M4F subsystem
is actuall identical on both SOCs.
Therefore, just add all missing CONFIGs, files, etc. to
support the AM6442x SOC.
Since MMR and RAT initialization are identical too, both
functions can be re-used. However, since they might
differ in the future, the am64x has it's own init
function.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
This implements basic driver to utilize the I3C IP block
on NPCX.
1. I3C mode: Main controller mode only.
2. Transfer: Support SDR only.
3. IBI: Support Hot-Join, IBI(MDB).
Controller request is not supported.
4. Support 3 I3C modules:
I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
1. The only valid values of MCLKD clock frequency
are between 40Mhz to 50Mhz.
2. If DMA is used, the APB4_CLK clock frequency must
be equal to or higher than 20Mhz.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Prevent the CPU from entering deep doze mode when JTAG debug is enabled.
Additionally, The CPU address from 0x80000800 to 0x800008FF should be
reserved for JTAG debug usage. This commit reserves the area from the end
of the reset section to 0x800008FF if JTAG debug is enabled.
Tested with:
- west build -p always -b it82xx2_evb samples/hello_world/
-DCONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE=y
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Real Time peripherals should be enabled by default.
Add a common initialization point for all VPRs and enable them.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
IRQ handling functions are now in interrupt controller.
Enable necessary KConfigs to support CLIC properly.
A nice side effect of enabling RISCV_PRIVILIGED is that
`vector.S` is no longer necessary as common code handles
that.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Fixed order of mepc and _mcause in esf for 32bit stacking.
Added missing stack pointer alignement bit support.'
Signed-off-by: Lukasz Stepnicki <lukasz.stepnicki@nordicsemi.no>
RISCV_PRIVILEGED implicitly depends on INCLUDE_RESET_VECTOR.
Remove that dependency by adding support for SoCs that
do not need the `__reset` stub.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
For more effective code execution on STM32 devices is convenient
to enable flash prefetch buffer.
To be enabled by default, possible to disable using kconfig.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Fixes#71511
Follow-up to #70977
Update the approach by moving the `PROVIDE` directive to a separate
linker script added using `zephyr_linker_sources()`. This makes the
change more likely to propagate to existing samples which are using
CONFIG_CUSTOM_LINKER_SCRIPT.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Move the cache size set calls from soc.c do common loader.c
for all related SOCs. Remove unnecessary includes.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The dependencies should be in a 'depends on' clause.
Also, 'depends on PTP_CLOCK' is redundant because this is
within 'if PTP_CLOCK' already.
Additionally, conditionally include the PTP header in the mac driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Variant chip has different USBPD HW PHY, so FW needs
to apply different downstream CONFIG settings based on
the PHY version.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Abderrahmane Jarmouni