Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and riscv,plic0. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
add device tree support for riscv32-qemu Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>