To un-block continuing of soc and board porting then move all socs and
boards and support building of updated docs then move all ported socs
and boards to their final location.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
To un-block continuing of soc and board porting then move all socs and
boards which have not yet been ported to boards_legacy / soc_legacy
folders.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Commit a10fee2d5e (drivers: clock_control: ccm_rev2: add support for
reclocking FlexSPI) introduced the ability to set the FlexSPI
clock frequency at runtime on RT11xx series SOCs. However, this
implementation resulted in the clock frequency being rounded up, not
down. This can result in flash clock frequency violations on some
flash parts, causing the system to crash when running in XIP mode.
Fixes#69088
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Executing from RAM sections other than rom/code should cause a fault.
This is tested as part of the kernel mem_protect tests.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Because both, RISC-V and ARM cores share the same pinctrl driver. The
top level common folder will disappear with the introduction of HWMv2,
where multi-arch SoCs will be well supported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Extend Kconfig definitions and nrfx_config translations so that UARTE
instances that are available in nRF54H20 can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
nrf-regtool is a Python utility from Nordic Semiconductor, which is used
for generating binary files with register values for given peripherals.
It sources the descriptions of peripheral registers from CMSIS-SVD files
(typically ones bundled with nRF MDK).
For some peripherals, such as UICR, nrf-regtool supports parsing values
from devicetree as well, based on the bindings already found in Zephyr.
Currently, this tool is not submitted as a script to Zephyr, but it can
be installed from PyPI.
Having nrf-regtool installed is recommended when working with nRF54H20.
Booting the Application or Radiocore CPU requires flashing not only its
firmware, but also its respective UICR instance. On this SoC, the UICR
is used to assign ownership of global hardware resources, including
memory and peripherals, to individual cores. The Zephyr build system can
call nrf-regtool to generate the UICR based on devicetree, to reflect
the boot-time hardware configuration required for a given application.
The generated `uicr.hex` is then merged with `zephyr.hex`, so that they
can be flashed together using west.
The build system integration takes the form of a CMake package, which
includes a version check and reusable components; over time, some of
these components can be reused by sysbuild. This package is located in
the `hal_nordic` module, because it depends on the `SOC_SVD_FILE` CMake
variable, which is defined there as well.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add nrfx and Kconfig related infrastructure plus SoC initialization
code to allow building for nRF54H20 targets (Application and Radio
cores).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... to cover missing __ICACHE_PRESENT and __DCACHE_PRESENT symbols that
should be defined in MDK files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for reclocking flexspi in ccm_rev2 driver. Clock update
functions are provided for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Consistently use `zephyr_library*` cmake functions for all nRF Series
and set the Cortex-M linker script in a common place for all of them.
Remove no longer needed include directories.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In nRF54L15 FICR can be accessed also from non-secure code,
so it does not have NRF_FICR_S defined.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
NRF_RTC_TIMER will not be a default timer in the next
version of Nordic timer. It should be soc selection specific.
Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
The RA_PINCFG macro is used to generate a value that can be written
directly to the pin function select register. In addition to the pin
function this value also contains port and pin number information,
located in bit fields that are unused by the register. The bit field
used to store the port information consists of 3-bits. However, a typo in
the mask definition limited the field to two bits meaning only ports 0-3
could be configured. This patch resolves the issue, allowing ports 0-7 to
be configured. If the port is greater than 7 another field (port4) is used
to store an additional bit (allowing an additional 8 ports to be
supported). However, use of this field has not yet been implemented.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Adds CAN drivers for XMC4xxx SoCs.
XMC4xxx has multiple CAN nodes. The nodes share a common clock and
a message object pool.
The CAN nodes do not have a loopback mode. Instead there is an
internal bus which can be used to exchange messages between
nodes on the SoC. For this reason tests/samples which rely on the
loopback feature have been disabled.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
ROM configures the ISP boot pins as gpio to determine what boot mode to
be in. But some ROM revisions have a bug where they do not restore the
reset state of these pins before booting application. This can cause
power leakage on these pins and is not an intended configuration from
Zephyr user/board point of view, so restore the reset state as part of
early SOC init (disable the pins). Configuration of pins should be
left up to app/board devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At chip startup, jtag pins are configured by default to enable
debug.
This configuration adds consumption and when using PM profile,
we can save ~40uA by resetting this configuration and setting pins
to analog mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
Jamie McCrae