SDA and SCL pins can now be configured through DTS.
Pins on development kits have been assigned according to arduino
headers.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
The i.MX 6SoloX SoC is a hybrid multi-core processor composed by one
Cortex A9 core and one Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A9 core (running Linux) via RPMsg.
The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README
The A9 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A9 can perform these steps at bootloader level after the Linux
system has booted.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
The various STM32 reference manuals sometimes define the USB endpoints
as IN or OUT only and sometimes as bidirectional, even in the same
manual. This is likely because the OTG implementation has one set of
registers for the IN endpoints and one other set for OUT endpoints.
However at the end a given endpoint address can both transmit and
receive data.
This causes some confusion how to declare the endpoints in the device
tree, and depending on the SoC, they are either the same number of IN
and OUT endpoints declared, or they are declared as bidirectional. At
the end it doesn't really matter given how the driver uses those values:
#define NUM_IN_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
CONFIG_USB_NUM_IN_ENDPOINTS)
#define NUM_OUT_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
CONFIG_USB_NUM_OUT_ENDPOINTS)
#define NUM_BIDIR_EP NUM_OUT_EP
This patch therefore cleanup the driver, the DTS, and the DTS fixups to
only define the number of bidirectional endpoints.
In addition to the cleanup, that fixes a regression introduced by commit
52eacf16a2 ("driver: usb: add check for endpoint capabilities"), which
introduced a wrong check for SoC only defining the number of
bidirectional endpoints.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit enables CAN on the STM32L432.
Tested on nucleo l432ck with external transceiver and loopback mode.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
This commit splits the common interrupt into rx and tx parts because
only STM32F0 series has a common interrupt.
Moved clock source definition to device-tree.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
The prepended 0x causes DTC warnings and shouldn't be there.
Tested by compiling hello_world for nrf52840_pca10056 before and after.
Fixes#8334.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
This adds basic support for declaring gpio nodes in dts for nrf52.
The dts.fixup provides mapping for the generated defines to the config
defines currently used by the nrf gpio driver.
Existing boards that use nrf52 are updated.
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
IRQ priorities for CAVS and DW were previously defined in Kconfig.
They are now defined via DTS and removed from Kconfig.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
This commit moves the bit timing (PROP, BS1, BS2 segments and SWJ)
from Kconfig to the device-tree and fixes issue #7933
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
ARC only supports only 2 priority levels so make sure
the IRQ priority is not greather than 1.
The test was passing in previous build because the ASSERT was
not enabled.
Fixes Issue #8099
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
"clocks" property is defined in st,stm32-u(s)art.yaml
files while aslo defined in uart.yaml.
Remove redundant information.
Fixes#7974
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Enable supporting UART4 on STM32F107 and STM32F103Xe SoCs.
Modified stm32f1/dts.fixup for replacing USART with UART.
Signed-off-by: Jun Li <jun.r.li@intel.com>
LPUART (Low-power UART) peripheral is just like ordinary U(S)ART
which lives in a separate clock/power domain.
Therefore already existing code could be reused as is
almost entirely.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Correctly process multiple include files given to the
!include command of the YAML loader.
The fix only targets the sequential definition of include files.
Fixes#7067
Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
The STM32L432 SoC has a standard non-OTG USB controller. Add an entry
for it in stm32l432.dtsi and add the corresponding DTS fixup entries.
The controller is kept disabled and should be enabled at the board
level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
USB OTG is currently enable for the whole STM32L4 family, while only a
few of them actually support it:
- STM32L475, STM32L476 and STM32L496 have an OTG controller
- STM32L432, STM32L433 and STM32L452 have an USB controller
- STM32L431, STM32L451 and STM32L471 do not have any USB controller
Fix that by moving the DT entry from stm32l4.dtsi to stm32l475.dtsi
and by adding a #ifdef #endif around the corresponding DTS fixup
entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
QMSI bindings were created prior to this base, and unfortunately not
updated to latest changes on last rebase.
Fixes#7694
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
patch add clock frequency and interrupt property to uart
node in intel_s1000.dtsi. Include soc.h after types.h to
prevent build error.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
The LSM6DSL accel/gyro sensor can be accessed through
SPI bus. So the required configuration can be passed through
dts file.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Fix the ns16550 uart driver and relevant SoCs accordingly.
All generic settings are now DTS based.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Fix the qmsi uart driver and relevant SoCs accordingly.
Also: using config for irq everwhere relevantly and not an hardcoded
value in the driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Get the name generated through dts as well.
Fix the rtc driver and relevant SoCs accordingly.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Get the name and irq flags generated through dts as well.
Fix Kconfig for the gpio driver accordingly.
Irq priority is not set by dts for D2000 as it's irq controller does
not support it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Zephyr exposes the ability to set IRQ priority on IOAPIC.
To keep compatibility with Linux, let's add the priority at the end
after sense. So imported dtsi with interrupt-cells set to 2 will work as
usual.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add driver for MCUX mailbox which can be used for lpcxpresso54114
and other lpc and kinetis socs.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add soc configuration support and dts files for nxp_lpc54xxx_m0.
Adjusted nxp_lpc54xxx soc, configuration and dts files for the
presence of slave core.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds dts bindings for the kinetis watchdog peripheral, and updates the
watchdog nodes for the k64 and kw2xd socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch adds some DTS information to flesh out the NXP Kinetis
based RTC blocks. DTS fixups were added as well to match up the driver
usage to the DTS output.
Signed-off-by: Andy Gross <agross@kernel.org>
Add use-prop-name to disconnect-gpios property in st,stm32-usb
yaml, in order to generate friendly name for the definitions.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Rename various SoC related defines and files from just being LPC54114
to LPC54114_M4. This is in prep for supporting a build for the second
core on the LPC54114 (the Cortex-M0+).
* Renamed Kconfig SOC_LPC54114 to SOC_LPC54114_M4
* Renamed Kconfig.defconfig.lpc54114 to Kconfig.defconfig.lpc54114_m4
* Introduced nxp_lpc54xxx_m4.dtsi based on nxp_lpc54xxx.dtsi
* Moved some pinmux related defines into SoC code.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Define reset-gpio and irq-gpio in zephyr,bt-hci-spi yaml, to
generate GPIO definitions for control pins of Bluetooth HCI
SPI module.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
* add gpio, i2c, spi definitions
* optimize and bug fix the dts.fixup
* optimize and bug fix the em_starterkit related definitions
in dts folder
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
- Changed define for SETTINGS_CONFIG_PAGE_SIZE from a hard coded value
to reference build system generated FLASH_ERASE_BLOCK_SIZE. This value
comes from 'erase-block-size' found in the dtsi file of devices.
- Modified nrf52840.dtsi to include definition for 'erase-block-size'
Fixes#7107
Signed-off-by: David Leach <david.leach@nxp.com>
Commit introduces support for watchdog configuration for Nordic
Semiconductor nRF SoCs in device tree.
Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
Adds dts bindings for the mcr20a wireless transceiver. The frdm_k64f
board supports the mcr20a via an Arduino shield, therefore the dts node
is added to the board dts. The kw2xd is a SiP and thus the mcr20a dts
node is added to the soc dts.
The networking samples using prj_frdm_k64f_mcr20a.conf have been broken
since the refactoring of the mcux gpio driver to dts in commit
4e8f29f319. The sample is now fixed.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds dts spi bindings for the kinetis dspi controller, and updates the
k64, kw2xd, kw40z, kw41z dts nodes accordingly.
Updates the dts interrupt priorities to match the board defconfigs
(e.g., boards/arm/frdm_k64f/Kconfig.defconfig)
For k64, fixes an error in the spi1 interrupt number and adds a third
instance (spi2).
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds dts bindings for the fxas21002 interrupt pins to all boards that
have this sensor.
The fxas21002 driver is currently only aware of one sensor interrupt
pin, therefore the routing of INT1 or INT2 to the driver is handled in
each board's dts.fixup.
The fxas21002 sample application has been broken since the refactoring
of the mcux gpio driver to dts in commit
4e8f29f319. The sample is now fixed.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds dts bindings for the fxos8700 interrupt pins to all boards that
have this sensor. The frdm_k64f and hexiwear_k64 connect both sensor
interrupt pins to the mcu, but the frdm_kw41z connects only one.
The fxos8700 driver is currently only aware of one sensor interrupt pin,
therefore the routing of INT1 or INT2 to the driver is handled in each
board's dts.fixup.
The fxos8700 sample application has been broken since the refactoring of
the mcux gpio driver to dts in commit
4e8f29f319. The sample is now fixed.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add a set of Kconfig symbols that allow us to set that the GPIO
driver/SoC support DTS (HAS_DTS_GPIO) and that drivers that need/use
GPIO support DTS as well (HAS_DTS_GPIO_DEVICE).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to generate GPIO definition for control pin of BlueNRG module
define reset-gpio and irq-gpio in st,spbtle-rf yaml binding.
Add HAS_DTS_SPI_PINS kconfig symbol to control use of the '#define'
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that we can generate gpio info from dts lets add optional support
fot the cs-gpios property in the bus controller node. This matches the
binding spec from Linux on how cs-gpios are handled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
'cell_string' yaml attribute has been introduced in order to
help enforcement of specific string during defines generation.
This adds complexity in understanding script behavior as a black
box and create additional dependency which is not strictly required.
For node specific generation functions (pinctrl and interrupts),
this could be replaced directly by an hardcoded version
(as everyone used the same 'cell_string' anyway).
For extract_cells functions, string could be replaced by extracted
property name. As a consequence, we're now able to generate defines
for properties refering to these controllers via phandle.
For instance, in following node
spbtle-rf@0 {
compatible = "st,spbtle-rf";
reg = <0>;
reset-gpios = <&gpioa 8 0>;
};
We'll be able to generate:
#define ST_STM32_SPI_...LE_RF_0_RESET_GPIOS_CONTROLLER "GPIOA"
#define ST_STM32_SPI_...PBTLE_RF_0_RESET_GPIOS_FLAGS_0 0
#define ST_STM32_SPI_..._SPBTLE_RF_0_RESET_GPIOS_PIN_0 8
Only impact for this whole change is for NXP clocks which were the
only ones using 'cell_string' attribute with a value different than
the default one.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds flexspi and semc memory controllers to the i.MX RT SoC. Adds
hyperflash, qspi, and sdram external memories to the mimxrt1050_evk
board.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Previously, when !CONFI_XIP, BOOTLOADER_SRAM_SIZE was defaulted
to 16 (K), reducing the size of SRAM available for the program.
Also, though it has no effect, the value for SRAM start in the
dtsi file was incorrect.
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
To prepare to upcoming dtc v1.4.6, fix warnings in dts files.
This commit addresses the following warning:
Warning (unit_address_vs_reg): Node /soc/pin-controller has a reg
or ranges property, but no unit name
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To prepare to upcoming dtc v1.4.6, fix warnings in dts files.
This commit addresses the following warning:
Warning (clocks_property): Missing property '#clock-cells' in node
/soc/rcc@40021000 or bad phandle (referred from
/soc/pin-controller/gpio@40011800:clocks[0])
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds gpio labels to all kinetis socs in preparation for refactoring the
mcux gpio driver to dts. The kl25z was missing gpio nodes altogether, so
they are added.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Create a dt-bindings/gpio.h file.
Bindings definitions are extracted from existing gpio.h.
gpio dt-bindings file is required because existing gpio.h file could
not be parsed by dts parser.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.
The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README
The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.
The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:
+---------------+-----------------+---------------------------+
| Memory Name | Start Address | Size |
+===============+=================+===========================+
| TCML | 0x007F8000 | 32KB |
+---------------+-----------------+---------------------------+
| TCMU | 0x20000000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM_S | 0x20180000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM | 0x00900000 | 128KB |
+---------------+-----------------+---------------------------+
| DDR | 0x10000000 | 256MB |
+---------------+-----------------+---------------------------+
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Adds a shim layer around the imx uart driver to adapt it to the Zephyr
serial interface.
Modem mode was introduce to control it as DCE and DTE and can be
configured in the device tree:
modem-mode:
type: int
category: required
description: Set the UART Port to modem mode 0 (dce) 1 (dte)
generation: define
For now only the UART 2 was tested.
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Add initial device tree support for the em{7,9,11}d SoC and associated
em_starterkit boards. The device tree at this point specifies cpu core,
memory, interrupt controller, uart's and i2c controllers.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This will generate the necessary configuration for the i2c controller
on quark_d2000.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will generate the necessary configuration for the 2 i2c controllers
on quark_se_c1000.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Applying the change to relevant arch/boards, either in their Kconfig or
the dts specific files.
Taking the opportunity in dw driver to rename the variable the same way
as they are everywhere else in the code (s/dev/dw and s/port/dev) in
init function.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will generate the necessary configuration for the i2c controller on
quark_x1000.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will generate the necessary configuration for the 2 i2c controllers
on quark_se_c1000_ss.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
With upcoming ICs that are not in the nRF5x family, rename the flash
driver and all its dependencies from nrf5 to nrf.
Should also fix the issue introduced by f49150cab6 which broke the
assignment of the flash device due to a partial rename.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Adds a driver for SX1509B I2C GPIO chip. This driver only supports the
basic GPIO features and does not currently implement the LED driver and
keypad matrix features.
Signed-off-by: Aapo Vienamo <aapo.vienamo@iki.fi>
Add initial support for STM32L073xZ SOC which is not very different
from already supported STM32L072xZ.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Since not all boards enable all devices, we typically have the SoC dtsi
file have a device marked with status = "disabled" and have the
board.dts explicitly enable with status = "ok". Update it so USB on
Atmel SAMD21 work this way.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added device tree support to the ARM SBCon I2C controller. We utilize
the compatiable "arm,versatile-i2c" the binding from Linux for the some
peripheral block.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch the SoC device tree to define a single entry per SERCOM instead
of one per mode.
Define a Device Tree binding for the SAM0 SPI and use it instead of
Kconfig for enabling / disabaling instances
Switch the Arduino Zero, Adafruit Feather M0 Basic Proto, and
Trinket M0 to use the new defintion.
Add the APA102 LED that's on the Trinket as a test.
Signed-off-by: Michael Hope <mlhx@google.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Implements interrupt driven UART for the serial driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Justin Watson <jwatson5@gmail.com>
The spi nodes should have #address-cells and #size-cells properties much
like i2c does. Add these missing properties.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Most STM32F429 SoCs have 6 SPIs, but STM32F429Vx SoCs only have
4 SPIs. This is one of the rare conditions where device-tree
directive /delete-node/ should be used.
Add spi5 and spi6 node to stm32f429.dtsi. Create file
stm32f429vX.dtsi to delete those nodes and document usage of
/delete-node/ directive.
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>