Commit Graph

26 Commits

Author SHA1 Message Date
Keith Packard 77554a09bb tests/x86/pagetables: Check pinned memory flags
Add another clause in the test_ram_perms code to verify that any pinned
regions have the correct flags.

Signed-off-by: Keith Packard <keithp@keithp.com>
2023-01-30 23:46:55 +00:00
Keith Packard 661ff0527f tests/x86: Check libc partition in page permissions test
Picolibc uses the libc partition for some variables, so make sure
the test allows references to that data.

Signed-off-by: Keith Packard <keithp@keithp.com>
2022-11-08 10:44:36 +01:00
Gerard Marull-Paretas 79e6b0e0f6 includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.

The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.

NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-09-05 16:31:47 +02:00
Fabio Baltieri def230187b test: fix more legacy #include paths
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2022-08-02 16:41:41 +01:00
Enjia Mai 6956364ec9 tests: arch: x86: move the test pagetables to new ztest API
Migrate the testsuite tests/arch/x86/pagetables to the new ztest API.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-01 06:28:56 -04:00
Gerard Marull-Paretas ade7ccb918 tests: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 20:02:14 +02:00
Torsten Rasmussen 3d82c7c828 linker: align _image_text_start/end/size linker symbols name
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.

The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end   -> __text_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen c6aded2dcb linker: align _image_rodata and _image_rom start/end/size linker symbols
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.

The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.

This commit align those names and prepares for generation of groups in
linker scripts.

The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end   -> __rom_region_end

The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end   -> __rodata_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Daniel Leung 6a58c34aa6 tests: x86/pagetables: limit permission test under demand paging
When demand paging is enabled and not all generic sections are
in physical memory at boot, only tests the permission up to the end
of the pinned section.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-26 21:16:22 -04:00
Torsten Rasmussen 1cccc8a8fe cmake: increase minimal required version to 3.20.0
Move to CMake 3.20.0.

At the Toolchain WG it was decided to move to CMake 3.20.0.

The main reason for increasing CMake version is better toolchain
support.

Better toolchain support is added in the following CMake versions:
- armclang, CMake 3.15
- Intel oneAPI, CMake 3.20
- IAR, CMake 3.15 and 3.20

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-20 09:47:34 +02:00
Daniel Leung 0a45691aeb tests: x86/pagetables: update test for boot and pinned sections
This updates the test to account for boot and pinned sections.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-05-10 16:00:43 -05:00
Andrew Boie 77861037d9 x86: map all RAM if ACPI
ACPI tables can lurk anywhere. Map all memory so they can be
read.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 61651976c2 x86: tests: pagetables: fix assumptions
All RAM may not be mapped. Check the mapping for the main kernel
image and the locore if it exists.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Andrew Boie 35ec07dfe0 tests: x86: pagetables: pass if userspace disabled
_app_smem doesn't exist in this case.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Anas Nashif 371c6d4142 Revert "tests: x86: pagetables: pass if userspace disabled"
This reverts commit 898621a1b4.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Anas Nashif 0d2724649e Revert "x86: tests: pagetables: fix assumptions"
This reverts commit a7d8b3385a.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Andrew Boie a7d8b3385a x86: tests: pagetables: fix assumptions
All RAM may not be mapped. Check the mapping for the main kernel
image and the locore if it exists.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Andrew Boie 898621a1b4 tests: x86: pagetables: pass if userspace disabled
_app_smem doesn't exist in this case.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Andrew Boie d5072d1378 tests: x86: pagetables: show user thread tables
Show the page table layout for a user thread. This
may be somewhat different from a supervisor thread
especially if KPTI is enabled.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-12-10 18:22:58 -05:00
Andrew Boie e51226b827 tests: x86: pagetables: use new Kconfigs
Don't use old SRAM macros for mapped virtual memory bounds.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-11-09 20:19:13 -05:00
Andrew Boie d2a72273b7 x86: add support for common page tables
We provide an option for low-memory systems to use a single set
of page tables for all threads. This is only supported if
KPTI and SMP are disabled. This configuration saves a considerable
amount of RAM, especially if multiple memory domains are used,
at a cost of context switching overhead.

Some caching techniques are used to reduce the amount of context
switch updates; the page tables aren't updated if switching to
a supervisor thread, and the page table configuration of the last
user thread switched in is cached.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-11-05 09:33:40 -05:00
Andrew Boie cdbf3aa27d tests: x86: pagetables: fix non-KPTI case
If KPTI is not enabled, then the US bit will be set for all
the default memory partitions in the _app_smem section.

The error printed when a mismatch occurs now shows the
expected flags.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-10-26 08:56:47 -04:00
Daniel Leung 9e0090d114 tests: x86/pagetables: skip table dumping if large memory
For boards with (relatively) large memory, the test which dumps
page tables takes a long time to finish. The default timeout of
sanitycheck is not enough for those boards. UP Squared board is
such a board. So limits to pagetable dumping to boards with
less than 32MB.

Fixes #28548

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-09-22 10:59:53 -05:00
Andrew Boie 7d32e9f9a5 mmu: support only identity RAM mapping
We no longer plan to support a split address space with
the kernel in high memory and per-process address spaces.
Because of this, we can simplify some things. System RAM
is now always identity mapped at boot.

We no longer require any virtual-to-physical translation
for page tables, and can remove the dual-mapping logic
from the page table generation script since we won't need
to transition the instruction point off of physical
addresses.

CONFIG_KERNEL_VM_BASE and CONFIG_KERNEL_VM_LIMIT
have been removed. The kernel's address space always
starts at CONFIG_SRAM_BASE_ADDRESS, of a fixed size
specified by CONFIG_KERNEL_VM_SIZE.

Driver MMIOs and other uses of k_mem_map() are still
virtually mapped, and the later introduction of demand
paging will result in only a subset of system RAM being
a fixed identity mapping instead of all of it.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-09-03 14:24:38 -04:00
Anas Nashif dca317c730 sanitycheck: inclusive language
change whitelist -> allow.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-27 07:04:07 -04:00
Andrew Boie 030456c24e x86: add pagetables test suite
For the moment, we validate the flags on all RAM pages,
ensure that NULL is never mapped, and show that dumping
page tables doesn't crash.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-08-25 15:49:59 -04:00