QMSI 1.1 Beta is available on Github:
https://github.com/01org/qmsi/releases/tag/v1.1.0-beta
Update the QMSI drop we maintain in Zephyr and
keep the modification to qm_soc_regs.h introduced on commit
6b88a6b945 "ext qmsi: Add USB base and interrupt defines" since
that patch hasn't made into the QMSI 1.1-Beta release in time.
Also, fix the build where needed:
- add hard dependency from qm_i2c to qm_dma
- fix spi_qmsi_ss.c due to new parameter naming
- fix adc_qmsi.c and adc_qmsi_ss.c due to a new parameter
Change-Id: I01388c787f5ee6ee97fece2e42b24a717522207f
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
SPI drivers for K64 is now using system log.
Change-Id: Ifd0d321e2ff84c581261b7cb3a7a4485afbd67f6
Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
JIRA: ZEP-311
This will allow the driver to be fiber and task safe
Jira: ZEP-410
Change-Id: I61d3d9e4128bae781f1c86c07af79eb6e43ebeda
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This will allow the driver to be fiber and task safe
Change-Id: I916d4ad67ab6f51f41f3d1136c105e4d1445de48
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
The TX fifo threshold is pretty arbitrary.
Set this too big and too many interrupts will occur
for no good reason. Set it too small, and latency
in the SPI transactions is introduced. User's will probably
have to tune this per their application and SPI frequency, etc.
I think setting this to 50% is a good guess for now.
Change-Id: Ib325d40bc7ee10473d99443b3b3cd00fd6e4b95f
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Convert leading whitespace into tabs in Kconfig files. Also replaced
double spaces between config and <prompt>.
Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add SPI sub-driver for sensor system.
Use SPI irq number definitions already in Zephyr header file.
Origin: Original
Change-Id: I215db3acc535093dd75c0817cbe5af77e6e76e16
Signed-off-by: Baohong Liu baohong.liu@intel.com
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
When using the Synopsys DesignWare Synchronous Serial Interface (SSI),
the FIFO depth can vary from 2-256, depending upon how this module is built.
For quark_se_ss, it was using a depth of 8. For EM Starterkit, it will be
32. Adding this now as a configurable option. A larger FIFO really helps
reduce SPI interrupts.
Change-Id: Id2bc8470bfc08ab447d38b89c7904cff010c63bd
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Just as rxftlr can be read, a macro is needed so that txftlr can be read.
Symmetry.
Change-Id: Id987f700d89268feca60850f4fdf512f990f3ab6
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
A recent submission caused a build error for DW
CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE because the symbols
CONFIG_SPI_<0,1>_IRQ went missing from Kconfig.
I think these should probably NOT be configurable, because
on an SOC, interrupt lines are hard. So I'm changing
the names back to SPI_DW_PORT_<0,1>_IRQ, with there
definitions originatig in the soc.h file.
Also, on DesignWare ARC EM Starterkit, the SPI interface
has 6 slave selects, but IP itself can handle up to 16.
Why does this start from 1 and not 0? Argh!
DBG_COUNTER_RESULT() should expand to 0 when not used.
Also, don't check version from DesignWare IP because
it can be different for each target.
spi_dw_isr() requires a cast when converting arg to dev.
Change-Id: I83d55e0405583e7cafab80b09cbef44e0f96fcb8
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Use the same Kconfig infrastructure and options for all SPI drivers.
Jira: ZEP-294
Change-Id: I7097bf3d2e1040fcec166761a9342bff707de4dd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Most of the values are SoC specific and come from the SoC definition,
not need to define them in Kconfig.
Jira: ZEP-294
Change-Id: I962ce36b7e2361ea77ae4178bb7c86c19a241c4e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Most of the values are SoC specific and come from the SoC definition,
not need to define them in Kconfig.
Jira: ZEP-294
Change-Id: I7688ca523915e3fa8a1d28dea7a1d84a66b39d56
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not have priority per IP, use one config instead.
Change-Id: Ieb2923d4749a294e2a1c677d47d56a14cee3f36d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add Kinetis SoC family and rename fsl_frdm_k64f to mk64f12.
This will allow adding new SoCs of the same family and the reuse of code
among SoCs of the family and series.
Change-Id: Iea1a663aef7ce0487f147bdd36f668bebe80deb5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Note that the failure case can only be reached when compiling
for ARC side of Quark SE. Otherwise, the code is never compiled
which reduces code size for other platforms.
Change-Id: Ic76890cbaf22da5c3563e056cba9b39615d3da0c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the assignment of driver_api to just before
the init function returns. This is in preparation to
make device_get_binding() return NULL if driver
initialization fails.
Change-Id: I69590c463b84877d250c63d4460b7e254b79c8b3
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SPI API states:
"max_sys_freq is the maximum frequency supported by the slave it
will deal with"
However, currently, for DW the max_sys_freq is a divider which confuses
the user.
This patch adds a small hack to allow users to use both dividers and
frequencies when configuring the bus. The only trade-off is one has to
use dividers for bus frequencies smaller than 65536Hz. However, since
most devices nowadays can run at clock frequencies more than 100kHz,
this is a good compromise.
Change-Id: I44386cc8ad501b08eeaf71bc7588661ff36e108b
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
Most of the SoC and board Kconfig use the same values for
driver initialization priorities. So refactor them, and
discard duplicate ones.
The shared IRQ init priority was changed so that the kernel
default init and device init priorities can be standardized
across all SoC/boards. Same goes for DesignWare SPI driver.
This also changes the UART_CONSOLE_PRIORITY and
IPM_CONSOLE_PRIORITY to UART_CONSOLE_INIT_PRIORITY and
IPM_CONSOLE_INIT_PRIORITY, to standardize across all drivers.
Note that this does not take away the ability to override
those values. This just provides reasonable defaults such
that there is virtually no need to override.
Change-Id: Ibbd95d802c637df06f9a2fd48763ee1e6f4ff627
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The base address, IRQ line, chip select numbers, and clock
gating constants are static per SoC, so there is no need to
make them configurable in Kconfig.
Change-Id: I9f87ca29c28c38c42d4e4f1a3a41fa231f63ef03
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Makes K64 spi driver submenu available only if K64 soc is
selected.
Change-Id: I0ada8863a592f056dbe48e78d9374f2348dcac14
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
() Moves config options for each controllers into their own
Kconfig files. This keeps upper level Kconfig from getting
too big.
() Options for each controller are moved under their own
submenus.
Origin: refactored from existing file
Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch replaces all occurences of the macro DEV_NOT_CONFIG by
-EPERM at the driver level. This patch is part of the effort to
transition from DEV_* codes to errno.h codes.
Change-Id: I3054c8aa76319a58a2eec089b8a72bf301c85391
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_USED by -EBUSY
at the driver level. So this patch touch the files under drivers/,
include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I21eb3ffe9bdfde98593dcf63c50a8bdcd376e49e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_INVALID_CONF by
-EINVAL at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: Idae0d5af8dd780416977c9261a5fb6188c3aab64
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_INVALID_OP by
-ENOTSUP at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I46aec3c65963018c479b01602e4a3eec8650eaff
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_FAIL by -EIO
at the driver level. So this patch touch the files under drivers/,
include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I0594ab5dbe667e074c250129e7c13ce512ac940f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_OK by the actual
value 0 at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I69980ecb9755f2fb026de5668ae9c21a4ae62d1e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
According to documentation, there must be at least one cycle delay
between two consecutive writes of the DR register. Apparently, this is
true for reading too, though undocumented.
The read_dr() inline function is called as follows:
*(spi->rx_buf) = read_dr(info->regs);
which the compiler, with full optimizations on, turns it into:
ld_s r2,[r1,24] <- the spi->rx_buf
sr 0x80000000,[r4] <- this is the strobe bit write !!!
lr r4,[r4] <- this is the FIFO read!!!
stb r4,[r2] <- store the result
Unfortunately, the read from the FIFO is always 0 since the FIFO data is
not yet available.
During my investigations, I found that the following code works:
sys_out32(1 << 31, info->regs + 0xd);
*(spi->rx_buf) = sys_in32(info->regs + 0xd);
This does, basically, the same thing. But the compiler inserts an
instruction in between the write/read:
sr 0x80000000,[r4] <- write of the strobe bit!!!
ld_s r2,[r1,24] <- the pointer goes to r2
lr r4,[r4] <- read from FIFO!!!
stb r4,[r2] <- store the result
A single clock cycle between writing the register and reading seems
to be enough for the data to become available for reading.
This patch adds a nop in the read_dr() inline function.
Change-Id: I0c216d5738d5771835b1052e2e83363e8e3abf0c
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
Support for Freescale/NXP K64 SPI modules, limited to:
- Master mode
- A single active set of clock and transfer attributes (CTAR0), which
includes non-adjustable delay parameters
- Tx FIFO fill and Rx FIFO drain interrupt handling
- Standard, continuous select and continuous SCK SPI transfer formats
Also, divide-by-zero code generation in this driver is prevented.
The 'volatile' attribute is added to some of the variables in the baud
rate and delay calculation functions of the K64 SPI driver in order to
prevent bad code generation by gcc toolchains for ARM seen when an
optimization setting above -O0 is used.
Specifically, a register is loaded with the constant 0 and is used as
the divisor in a following divide instruction, resulting in a
divide-by-zero exception.
This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain)
and 5.2.0 (the Zephyr SDK toolchain).
Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
There's no reason to require callers to cast their data to uint8_t *
when the data might e.g. originate in a packed struct or some other
data type. Instead, be nice to callers and let them use any pointer
they want. Additionally, declare the TX buffer as a const pointer so
unnecessary typecasts aren't needed for that either (if the data
originates in a const location).
Change-Id: I1482ca4e350b5a7fbda6871ed9f54f255af3aa9e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This log is in spi_intel_configure, not in spi_intel_transceive.
Change-Id: I5d62dd63d0cfa2c86f2dd5f9a6d367b7ad47b355
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The buffers aren't guaranteed to be aligned so that they're always
aligned for uint16_t or uint32_t data. Use the available unaligned
access macros to read/write the data.
Change-Id: Ie87c108aa370af196b9c759b59ed7fb9d1ed6183
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
When configured at a frequency of 2MHz, a transaction writing
3 bytes and reading 1 byte fails silently (last byte cannot be
read back from the device). Enabling CONFIG_SPI_DEBUG fixes the
issue.
Scope traces show that the transaction (from /CS assert to /CS
deassert) takes 14us and there is activity on the MOSI line
after /CS is deasserted. A transaction writing 2 bytes and reading
3 bytes take 22us.
The issue is due to the fact that completed() deasserts /CS after
the driver has put 3 bytes in the TXFIFO and taken 1 byte from RXFIFO.
Just because the last byte made it to the TXFIFO, it doesn't mean that
it was put on the MOSI line.
The fix:
For a transaction sending T bytes and expecting R bytes, let N=max(T,R).
Send exactly N bytes and wait for exactly N bytes (or an error). This
way, we are sure that all the bytes were sent to the target device.
Also:
Stop calling pull_data() after every byte sent, it might take a while
for a byte to show up in RXFIFO.
If RFS bit is set, stop sending bytes (will be really useful with a
bigger RFT).
Flushing RXFIFO in spi_intel_transceive() is not needed anymore.
Change-Id: Ifb06a12b03e3e20d6ace4d9f3a20fc11ec3bb010
Signed-off-by: Vlad Lungu <vlad.lungu@windriver.com>
Remove semicolon that triggers a build failure
when CONFIG_SPI_INTEL_PORT_1=y
Change-Id: Iea49d44059377cf9eb0b5b5e14b625cb316a65bb
Signed-off-by: Vlad Lungu <vlad.lungu@windriver.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/spi/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.
It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.
Change-Id: Ic992749b3210ed8a2e454edece41ceca5edbaf2e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This patch fixes the QMSI SPI shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in spi_qmsi_init() because the macro QM_SPI_MST_1
and the function qm_spi_master_1_isr are not defined in QMSI headers
from Quark D2000.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: Ic6e2f7f5a2c3f350ddf360b23ffab6b812948572
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Currently we have devices named "dw_spi_0" and "intel_spi_0" etc, which makes
it difficult for an application to look up. Or worse, forcing a 3rd party IP
to hardcode in support for only one specific IP block.
Change-Id: Ie485e2350b171b66b22cd7ab39e0fcd196f38af8
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Looking at all structs as to where we can pack them a little better, and
calling out the padding/stride at the end for future expansion.
Change-Id: I4a651092e950dd3d915af9fa0ee0d7d59803e58f
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Available only when CONFIG_SPI_DEBUG is set:
- Print out all exported functions with relevant infos
- Remove superfluous messages
- Make counter in push/pull not being instanciated when not debugging
Change-Id: Iaa96a897008d360a14bc83da54152c264f42c60d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It's a bug that did not happen, but is a valid one:
if there is an error, we should not care at all about current stage of
transmission, thus it will stop right away.
Change-Id: Iec2b519d8118233f570ded18d6c6eb4084371e5b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There are situations when the transfer starts before we have the time to
enable the CS line, so to be sure, we active it before even attempting
to start the transfer.
This fixes an CC2520 driver initialization issue using the QMSI SPI driver.
Change-Id: Ib9b324b77260ac537f714376c8056b1543e7e3b3
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Jesus Sanchez-Palencia