When CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y, we also
need to add -Xunaligned option for mdb to enable unaligned
memory access feature for nsim.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
* add toolchain abstraction for coverage
* add select HAS_COVERAGE_SUPPORT to kconfig
* port gcov linker code to CKake for arc
* give user permission to gcov bss section
* expand the size of iccm and dccm to 1M
Signed-off-by: Jingru Wang <jingru@synopsys.com>
Instrs_per_pass option specify the number of instructions excuted
before simulator switches operations. the default value is 512. If we
specify a small value for it the debugger's overhead will increase
significantly for simulation because of the time taken to rapidly
switch operations. And the overhead will cause some time critical
task failure.
Restore instrs_per_pass value from 10 to default 512, we will have a
good sanitycheck result for nsim_hs_smp.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
In PR #26836, we switch nSIM from custom legacy ARC UART model
to ns16550 model, which will allow us to use zephyr images build for
nSIM on other platforms like HAPS, QEMU, etc...
In PR #27334, which introduce new board nsim_em7d_v22, has gone
parallel to the switch to dwuart, and is still using legacy model.
With wrong configuration, the uart for nsim_em7d_v22 has no output,
which cause all tests failure.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Typically we have ARC core configurations where Fast IRQs (FIRQ) are
enabled together with multiple register files and those we have covered
by testing. But FIRQ & single register bank we only happen to have on
the older EMSK v2.2.it might be a good idea to add a similar
configuration to nSIM "boards" so that we keep it tested regularly.
nsim_em7d_v22 configuration is similar with em_staterkit_em7d_v22,
both configed with FIRQ & single register bank.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Switch nSIM from custom ARC UART to ns16550 model. That will
allow us to use zephyr images built for nSIM on other platforms
like HAPS, QEMU, etc...
This patch do:
* switch nSIM board to ns16550 UART usage
* change nSIM simulator configuration to use ns16550 UART model
* drop checks for CONFIG_UART_NSIM in ARC code
* update nSIM documentation
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
* current supported boards:
* emsk, iotdk, nsim, emsdp, hsdk.
* for the unsupported future boards, pls take a
reference of supported boards' board.cmake.
* mdb runner is required and the default runner for SMP
case, e.g., HSDK and nsim_hs_smp.
* other ARC boards can also choose to use mdb by
setting runner as mdb, e.g. west flash --runner mdb.
* with mdb runner, user can make a debug through mdb gui
* with arc_nsim or opencod runner (default runner), user
can make a debug through gdb cmdline.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Now when SMP support for ARC is available we may introduce a simulation
platform which might be used for testing & development for SMP setups.
One important note is stand-alone nSIM (as well as its "Free" flavour)
doesn't support SMP simulation so we have to switch to use of nSIM via
proprietary MetaWare debugger [1] and so:
1. We introduce new emulation target "mdb"
2. It's only possible to run that platform for those who
have MetaWare tools installed and valid license.
Though QEMU port for ARC is in work at the moment and once we
open that port and it has SMP support we'll switch to it and everybody
will be able to try ARC HS with SMP.
[1] https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
ARC nSIM simulates pretty much any modern ARC core,
moreover it emulates a lot of different core features so
it is possible to play with them even wo real hardware.
Thus we add yet another ARC core family to be used on simulated
nSIM board.
For now it's just a basic configuration with ARC UART for
smoke-testing of Zephyr on ARC HS CPUs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This will give us a possibility to check unaligned read/write support
in simulation.
Note nSIM with S(ecure)EM (with secure option) doesn't support that
mode in HW.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
ARC nSIM simulates all flavors or ARC cores so there's
no point in limiting its usage to ARC EM family only.
Moreover with upcoming addition of ARC HS family support
in Zephyr we'll be re-using nSIM "board" for them as well.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Watson Zeng