hsdk has an on board cy8c95xx I/O expander, and 4 on
board LEDs use the expander GPIO. Add the I/O expander
and LEDs in hsdk dts, then add documents for them.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
As of today the build-only testing in upstream is enabled for
nsim_em and nsim_em7d_v22 which are very similar from the
compiler POW. The ARC HS, ARC Secure EM and SMP targets miss
any testing.
So adjust default testing for better coverage by enabling
build-only testing for nsim_hs, nsim_sem and nsim_hs_smp and drop
excessive testing for nsim_em7d_v22.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Don't allow user to choose CPU_ARCEM / CPU_ARCHS options
but select them when exact CPU type (i.e. EM4 / EM6 / HS3X/ etc)
is chosen.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
When CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y, we also
need to add -Xunaligned option for mdb to enable unaligned
memory access feature for nsim.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Remove SPI_[0-8] and SPI_[0-8]_OP_MODES Kconfig symbols as no driver
uses them anymore. We also cleanup board and sample code to remove
use of these symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With addition of icount support ARC QEMU is now stable,
so we can finally enable it as default test platform.
This reverts commit 7d10b68baa.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
This allows to get much more reproducible results in terms of
amount of tests passed & failed.
But note it requires QEMU for ARC with icount support!
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* add toolchain abstraction for coverage
* add select HAS_COVERAGE_SUPPORT to kconfig
* port gcov linker code to CKake for arc
* give user permission to gcov bss section
* expand the size of iccm and dccm to 1M
Signed-off-by: Jingru Wang <jingru@synopsys.com>
In newer OpenOCD version from Zephyr's SDK v0.12, there are some
changes in OpenOCD scripts: JTAG probe interface (AKA "adapter")
setup, see http://openocd.zylin.com/#/c/5784/
And so we need to change OpenOCD scripts accordingly to match
newer OpenOCD version from Zephyr's SDK v0.12.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
OpenOCD cofig command: ftdi_device_desc description provides the
USB device description (the iProduct string) of the adapter. And If not
specified, the device description is ignored during device selection.
In newer OpenOCD version from Zephyr's SDK v0.12, there are some
changes in OpenOCD scripts.
In file interface/ftdi/digilent-hs1.cfg, ftdi_device_desc will be set to
"Digilent Adept USB Device", while we get the iProduct string
"Digilent USB Device" from em_starterkit adapter. it's better not
specify it and only use the vid and pid of the adapter for selection.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
XIP (eXecute In Place) is a method of executing programs directly
from long term storage (i.e flash memory). It allows us to
avoid copying text it into RAM, saving writable memory for dynamic
data and not the static program code.
We don't have such non-volatile memory capable for executing in
place on HSDK so we load Zephyr image to DDR memory with debugger
each time.
Disable XIP option for HSDK as we don't need it.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
On introduction of a "simplified" HSDK configuration where we only
use 2 cores out of 4 (in assumption that it will be working much
more reliably) we excluded a bit too much of details from OpenOCD script.
In particular we stripped not-used cores from JTAG chain description
which made OpenOCD quite unhappy:
----------------------------->8----------------------------
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: arc-em.cpu2 tap/device found: 0x200c24b1 (mfg: 0x258 (ARC International), part: 0x00c2, ver: 0x2)
Warn : JTAG tap: arc-em.cpu2 UNEXPECTED: 0x200c24b1 (mfg: 0x258 (ARC International), part: 0x00c2, ver: 0x2)
Error: JTAG tap: arc-em.cpu2 expected 1 of 1: 0x200424b1 (mfg: 0x258 (ARC International), part: 0x0042, ver: 0x2)
Info : JTAG tap: arc-em.cpu1 tap/device found: 0x200824b1 (mfg: 0x258 (ARC International), part: 0x0082, ver: 0x2)
Warn : JTAG tap: arc-em.cpu1 UNEXPECTED: 0x200824b1 (mfg: 0x258 (ARC International), part: 0x0082, ver: 0x2)
Error: JTAG tap: arc-em.cpu1 expected 1 of 1: 0x200024b1 (mfg: 0x258 (ARC International), part: 0x0002, ver: 0x2)
Info : JTAG tap: auto0.tap tap/device found: 0x200424b1 (mfg: 0x258 (ARC International), part: 0x0042, ver: 0x2)
Info : JTAG tap: auto1.tap tap/device found: 0x200024b1 (mfg: 0x258 (ARC International), part: 0x0002, ver: 0x2)
Error: Trying to use configured scan chain anyway...
----------------------------->8----------------------------
That lead us to the situation when the target cores were programmed
in a wrong way effectively failing all tests. Fixing it now.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
During review of ARC port of OpenOCD some changes were requested
in particular:
1. L2 cache (SLC in ARC parlance) semantics, see
http://openocd.zylin.com/#/c/5688/
2. JTAG probe interface (AKA "adapter") setup, see
http://openocd.zylin.com/#/c/5784/
And so we need to change OpenOCD scripts accordingly to match
newer OpenOCD version from Zephyr's SDK v0.12.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
nsim_hs_smp has 2 cores, and CONFIG_MP_NUM_CPUS defalut value is 2.
But some tests will have extra config: CONFIG_MP_NUM_CPUS=1, so we
need to launch cores according CONFIG_MP_NUM_CPUS, not using a fix
number 2.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Instrs_per_pass option specify the number of instructions excuted
before simulator switches operations. the default value is 512. If we
specify a small value for it the debugger's overhead will increase
significantly for simulation because of the time taken to rapidly
switch operations. And the overhead will cause some time critical
task failure.
Restore instrs_per_pass value from 10 to default 512, we will have a
good sanitycheck result for nsim_hs_smp.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Update nsim board documentation:
* add info about run on HW (HAPS)
* update info about dependencies in case of single / multi core
runs in simulation and run on HW
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
ARC nSIM boards (starting with nsim_ prefix) allow to run
Zephyr in simulator and on real hardware.
Allow to run Zephyr on HW by enabling mdb-hw runner.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
mdb runner is quite special as it can be used to run Zephyr on
both simulator (nSIM) and real hardware.
However it is really misleading as same command (west flash)
will run Zephyr in simulation for one board and try to run it
on HW for another board. Things are getting worse for boards
supporting both runs in simulation and on real hardware.
Let's split mdb runner for mdb-hw (for runs on HW) and mdb-nsim
(for runs in simulation) runners.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
align kconfig option CONFIG_ARC_CUSTOM_INIT to
CONFIG_INIT_ARCH_HW_AT_BOOT. Remove unused CONFIG_ARC_CUSTOM_INIT in
kconfig.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
UART IP is clocked with 50MHz on HAPS by default. So switch
UART clock-frequency from 100MHz to 50MHz for nsim_* boards
so the binaries can be run on HAPS as well.
This property is dummy in case run in simulator (nSIM) so we
don't need to change anything in nSIM configuration files.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
In PR #26836, we switch nSIM from custom legacy ARC UART model
to ns16550 model, which will allow us to use zephyr images build for
nSIM on other platforms like HAPS, QEMU, etc...
In PR #27334, which introduce new board nsim_em7d_v22, has gone
parallel to the switch to dwuart, and is still using legacy model.
With wrong configuration, the uart for nsim_em7d_v22 has no output,
which cause all tests failure.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
EMSK boards can't be reset between tests due to hardware configures.
MPU v3 configs in previous test could cause exceptions in the following
tests. This commit fixes this issue by restoring MPU registers initial
states at early init stage.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
Enable MWDT toolchain in sanitycheck for all ARC nSIM boards
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
add 2 cores configuration for
* who want to use 2 cores
* sanitycheck tests, as we found there are
difference between 2 cores and 4 cores, see
report in issue #26794
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
let mdd runner connect connect cores according to CONFIG_MP_NUM_CPUS,
e.g.
* CONFIG_MP_NUM_CPUS = 2, just connect 2 cores
* CONFIG_MP_NUM_CPUS = 1, just connect 1 core
* CONFIG_MP_NUM_CPUS = 4, connect all 4 cores
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Typically we have ARC core configurations where Fast IRQs (FIRQ) are
enabled together with multiple register files and those we have covered
by testing. But FIRQ & single register bank we only happen to have on
the older EMSK v2.2.it might be a good idea to add a similar
configuration to nSIM "boards" so that we keep it tested regularly.
nsim_em7d_v22 configuration is similar with em_staterkit_em7d_v22,
both configed with FIRQ & single register bank.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
* add toolchain abstraction for coverage
* add select HAS_COVERAGE_SUPPORT to kconfig
* port gcov linker code to CKake for arc
Signed-off-by: Jingru Wang <jingru@synopsys.com>
* to avoid confusion, combine nsim and mdb related
cmake configurations.
* this also enable the lanuch of mdb in sanitycheck
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
For true mmio-sram, arc,iccm, arc,dccm nodes we should not be setting
device_type = "memory". This should be used for true DRAM regions of
memory and not on SoC SRAMs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch nSIM from custom ARC UART to ns16550 model. That will
allow us to use zephyr images built for nSIM on other platforms
like HAPS, QEMU, etc...
This patch do:
* switch nSIM board to ns16550 UART usage
* change nSIM simulator configuration to use ns16550 UART model
* drop checks for CONFIG_UART_NSIM in ARC code
* update nSIM documentation
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The generic SPI GPIO chip select support now respects devicetree flags
for signal active level. Update all cs-gpios properties to specify
active low.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Instead of endlessly repeating the same command line args,
centralize this and tune the shift value on a per-board
basis.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
With latest SDK release v0.11.3 basic SMP support for HSDK
board was introduced in OpenOCD. Lets enable smp in openocd.cfg,
so using west we would be able to run Zephyr on all 4 cores.
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
* current supported boards:
* emsk, iotdk, nsim, emsdp, hsdk.
* for the unsupported future boards, pls take a
reference of supported boards' board.cmake.
* mdb runner is required and the default runner for SMP
case, e.g., HSDK and nsim_hs_smp.
* other ARC boards can also choose to use mdb by
setting runner as mdb, e.g. west flash --runner mdb.
* with mdb runner, user can make a debug through mdb gui
* with arc_nsim or opencod runner (default runner), user
can make a debug through gdb cmdline.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
emsdp_em7d_esp is a board with secure just like em_starterkit_em7d,
but the secure feature not configed in defconfig file. we need to add
below configs in emsdp_em7d_esp_defconfig files:
CONFIG_ARC_HAS_SECURE=y
CONFIG_TRUSTED_EXECUTION_SECURE=y
when secure feature enabled, we use secure timer for system tick, so
we need to add below macro for secure timer:
#define IRQ_SEC_TIMER0 20
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Now when we're finally ready to open QEMU port for ARC
we introduce the first ever platform it supports and in fact does
that quite well - Zephyr RTOS.
For now we only offer support of basic EM & HS code execution,
built-in timers, interrupt controller and set of very simple
peripherals: DW UART & optionally MMIO Virtio devices.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Watson Zeng