Commit Graph

4 Commits

Author SHA1 Message Date
Kumar Gala 900974362d dts: arm: Remove label property from devicetrees
Label properties are not required.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-27 18:48:10 +02:00
Aymeric Aillet 14ff2b1f88 drivers: clock: rcar: Deploy a driver for each soc
This commit rewrite renesas R-Car clock driver in order
to be able to support any new SoC easier.

This work is so creating a clock driver per soc alongside a
common driver for all reneasas r-car boars.

- drivers: create a driver per soc
  - create a common driver
  - create a common header used by soc & common driver
  - create a soc specific driver calling for common driver

- dts: use new compatible
  - use old yaml as common yaml
  - create a new "child" yaml to define the new compatible field
  - change compatible in device tree

As in Linux, the driver can support both r8a77951 and r8a77950
SoC's so we decided to name the new driver as in Linux with Zephyr
prefix : "clock_control_r8a7795_cpg_mssr.c".

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-06-28 18:11:44 +02:00
Aymeric Aillet d8f66b7343 dts: rcar: Rework clock definition
This commit is reworking clock definition in
order to match linux filetree and definition
as much as possible.

- dt-bindings: rework renesas clocks dt-bindings
  - regroup renesas related dt-bindings in a folder
  - rename renesas rcar common dt-binding to match linux name
  - add soc specific dt-binding matching linux name
  - soc dt-bindings are defining clocks matching linux names

- dts: use new clocks names
  - move clocks definitions in SoC layer for each core clock entry

- driver: use new clocks names

As seen in this commit, we are declaring clocks for "R8A7795" SoC
to match linux names.
Linux is not declaring "R8A77951" SoC specific files because
its also supporting the first H3 SoC version numbered "R8A77950".

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-06-28 18:11:44 +02:00
Julien Massot dc26d6bb4a soc: arm: add Renesas rcar_gen3 series support
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.

- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2

Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).

This first SoC definition is just enough to print Hello World in a
ram console.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00