Commit Graph

13 Commits

Author SHA1 Message Date
Marti Bolivar f4c3163d3b arch: riscv32: provide a general mechanism for saving SoC context
RISC-V permits myriad extensions to the ISA, any of which may imply
additional context that must be saved and restored on ISR entry and
exit. The current in-tree example is the Pulpino core, which has extra
registers used by ISA extensions for running loops that shouldn't get
clobbered by an ISR.

This is currently supported by including pulpino-specific definitions
in the generic architecture code. This works, but it's a bit inelegant
and is something of a layering violation. A more generic mechanism is
required to support other RISC-V SoCs with similar requirements
without cluttering the arch code too much.

Provide that by extending the semantics of the existing
CONFIG_RISCV_SOC_CONTEXT_SAVE option to allow other SoCs to allocate
space for saving and restoring their own state, promoting the
currently pulpino-specific __soc_save_context / __soc_restore_context
routines to a RISC-V arch API.

The cost of making this generic is two more instructions in each ISR
to pass the SoC specific context to these routines in a0 rather than
just assuming the stack points to the right place. This is minimal,
and should have been done anyway to keep with the ABI.

As a first (and currently only in-tree) customer, convert the Pulpino
SoC code to this new mechanism.

Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-12-04 22:54:23 -05:00
Nathaniel Graff 078f6098e2 soc/sifive-freedom: Use DTS to generate PLIC addrs
Describe the MMIO register regions for the PLIC in the DTS instead of
hardcoded in soc.h

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-04 07:48:27 -06:00
Nathaniel Graff 8907c09fee soc/miv: Use DTS to generate PLIC addresses
Describe the MMIO register regions for the PLIC in the DTS instead of
hardcoded in soc.h.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-04 07:48:27 -06:00
Andrzej Głąbek 20202902f2 dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig
These changes were obtained by running a script  created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:

1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
   #define X Y)
3. Check if that name is also the name of a Kconfig option
   3.a If it is, then do nothing
   3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
       has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
   (.c, .h, .ld)

Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.

Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 10:44:42 -06:00
Andrzej Głąbek f39ba7230d dts_fixups: Update labels generated from DTS with DT_ prefix
All labels containing "_<8-hex-digits>_" or "16550_<3or6-hex-digits>_"
in their names, assumed to be generated by the extracting script,
are updated with the DT_ prefix, to reflect the recent changes made
to the script.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 10:44:42 -06:00
Anas Nashif c2c6a6a245 qemu_riscv32: use hifive1 configuration
Use hifive1 configuration for this qemu and set
SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000

Fixes #10043

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-11-05 11:00:38 -05:00
Kumar Gala 751b02a49c drivers: serial: uart_miv: Convert to use DTS
Update the uart_miv driver to get params like name, addr, baud-rate,
clock freq from DTS generated defines.  Fixup related board and soc code
as needed.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-03 06:58:23 -04:00
Kumar Gala 11cb8778c7 riscv: Add min dts support for miv SoC & m2gl025_miv board
Add minimal DTS support for the m2gl025_miv.  The dts just has the core,
SoC, PLIC, and UART described.  We still get memory related info from
Kconfig.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-03 06:58:23 -04:00
Sebastian Bøe 8eb734cd82 DT: Rename from dts.fixup to dts_fixup.h
The Zephyr configuration system uses many different files in many
different formats. It makes it a lot easier for users to understand
what these files do if when we use the correct file extensions.

To this end we rename the dts.fixup files to the correct file
extension '.h'.

This is a breaking change for out-of-tree fixup files. Such files will
be detected and given an appropriate error message.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-10-08 11:38:56 -04:00
Kumar Gala 11e98fa925 riscv32: sifive-freedom: Move dts.fixup into soc dir
The dts.fixup for the hifive1 board was not board specific but related
to the SoC.  Move the dts.fixup into the SoC dir so any other boards
using this same SoC will take advantage of it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-05 13:21:49 -05:00
Kumar Gala db2ca70a23 dts: pulpino: Add device tree support for GPIO controller
Add the needed bits to get device tree support for the GPIO controller
on the Zedboard-Pulpino.  This will allow us to move LED & button info
into the board.dts.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-04 07:48:32 -05:00
Kumar Gala be4f53fa50 riscv: Add device tree support to pulpino
Add simple device tree support for the Pulpino SoC and Zedboard-Pulpino
board port.  This gets the UART info from device tree instead of soc.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-04 07:48:32 -05:00
Anas Nashif 279cc2e448 riscv32: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00