The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.
Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.
This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.
Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.
This also addresses the following issues:
() UART driver for Atmel SAM3 currently does not support interrupts.
So remove the code from vector table. This will be updated when
there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.
This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).
Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Clockgating was disabled for RTC and disabling RTC had no
effect on Quark SE boards.
Change-Id: I67448d5582a206fc7a68d763d504e9f743043b53
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
ia32/soc.h is only used by QEMU, but QEMU's INTx routing does not follow
the "standard design consideration".
Instead, the pins are swizzled based on the PCI slot. They are then
routed to IRQs based on the PIIX PIRQ configuration.
For simplicity use hard-coded values for the PIIX PIRQ configuration,
though it may be desirable in the future to determine these dynamically.
Also change the number of PCI buses to 1 and remove irrelevant comments.
Change-Id: I1592009a43dd8a9c5a7c54788fba52f14687ba35
Signed-off-by: Ido Yariv <ido@wizery.com>
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.
Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.
Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
That implementation is not galileo-specific, but rather a generic way of
rebooting an x86 target. Needs SoC support.
Change-Id: I9c3374a8ab57a624d9d9b7090260c5b11fe4e773
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/i2c/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.
It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.
Change-Id: If3c260b9a2fa095de47a99eb7fa5b947efefe9b1
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/spi/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.
It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.
Change-Id: Ic992749b3210ed8a2e454edece41ceca5edbaf2e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/gpio/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.
It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.
Change-Id: Id00f7907fa55025011dabce6e282a9623be23831
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch fixes the QMSI SPI shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in spi_qmsi_init() because the macro QM_SPI_MST_1
and the function qm_spi_master_1_isr are not defined in QMSI headers
from Quark D2000.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: Ic6e2f7f5a2c3f350ddf360b23ffab6b812948572
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/watchdog/Kconfig because 1) most
of the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig (e.g. arch/x86/soc/quark_d2000/Kconfig).
For Quark D2000, the IRQ priority options (WDT_DW_IRQ_PRI and WDT_QMSI_
IRQ_PRI) values are set to '0' since the priority information is ignored
by the interrupt registering system (the interrupt vectors are fixed in
this SoC).
Change-Id: I8f36c0f0e56211cdee3f2c6fc90c7dcac0a1b5aa
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/rtc/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig (e.g. arch/x86/soc/quark_d2000/Kconfig).
For Quark D2000, the RTC_IRQ_PRI default value is set to '0' since the
priority information is ignored by the interrupt registering system
(the interrupt vectors are fixed in this SoC).
Change-Id: I70de889cfd22e65f0e7acf7e57ddc6439f028394
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The name already set by the driver's Kconfig is correct, so overriding
it only causes confusion.
Change-Id: Ia6405786fdfdf103c922517c8140a07a9de387e0
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This patch fixes the GPIO QMSI shim driver so we are able to use it in
Quark D2000 based platforms. To enable this driver we have to add a few
#if guards because some macros and functions (e.g. QM_AON_GPIO_0 and
qm_aon_gpio_isr_0) are not defined in QMSI headers from Quark D2000
(this SoC doesn't support the Always-On GPIO controller).
This patch also adds the QMSI driver default options to arch/x86/soc/
quark_d2000/Kconfig.
Change-Id: Ia16a345e1de3008f167ed66f891834607c05f4a2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This adds support to the AON GPIO controller using the QMSI driver.
In order to enable it, the following configuration options must be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="PATH TO LIBQMSI"
CONFIG_GPIO_QMSI=y
CONFIG_GPIO_QMSI_AON=y
Change-Id: I5a1a232d97741ad7fdbf40d8aea5a835e5b4e724
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This adds a NULL check against the reset vector for ARC.
If the reset vector is null, do not start the ARC core
as there is nothing to execute, and will probably cause
the whole SoC to stall.
Change-Id: I78d77b3e5940a205e05c13369f889cf9c5955487
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch changes both Quark SE and D2000 Kconfig files to enable the
WDT_DW driver by default if the WATCHDOG is enabled. This way, we keep
it consistent with the approach we already follow for others peripheral
drivers (GPIO, I2C, SPI).
Change-Id: I9d8b81c0e659b1408137deb71e33dacf6d4108c2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch changes both Quark SE and D2000 Kconfig files to enable the
RTC_DW driver by default if the RTC is enabled. This way, we keep it
consistent with the approach we already follow for others peripheral
drivers (GPIO, I2C, SPI).
Change-Id: I4910e501c105b6218d046080c47b1e7a42eced92
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch fixes the QMSI I2C shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in i2c_qmsi_init() because the macro QM_I2C_1
is not defined in QMSI headers from Quark D2000.
Since this drivers is now properly tested with Quark D2000, this patch
sets the QMSI driver default options in arch/x86/soc/quark_d2000/Kconfig.
It also adds the wiring information required to test the i2c_lsm9ds0
sample app in the Quark D2000 CRB.
Change-Id: I4be03c09304da5a66ac663e48b1d72225eb5651d
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
In case the I2C_QMSI driver is selected by the user, enable both I2C
contollers by default. This is the default behavior for I2C_DW driver
as well.
Change-Id: If3dc8eb0a266fde7f598f7b12370e5be903aafed
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Always use braces, even on one-line code blocks.
Change-Id: Ic9e60db7f851d2fbee5bfd79cd810df23c0c5db0
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is part of an ongoing development of power management
support in zephyr. This implementation builds upon an existing
hook interface and adds more enhancements. This was tested
with reference implementations on quark_d2000 and quark_se.
Change-Id: I28092b7ec90ce1f1cc661cf99ca88708910c8eb2
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Renamed functions and labels used in power management code
according to coding convention. Only doing this to relevant
functions and not touching functions that will be removed in
future patches.
The stack used during resume would be necessary so
renamed that too.
Change-Id: I2f09a349b0f0fd6520c11b4cd73f4c8e1a13f100
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
GlobalTss is not defined anywhere. This was originally designed
to be used by power management code to switch thread context to
kernel resume location. An alternative to this method would be
implemented.
Change-Id: I9ae14ba14f9573d8bd8579869cdee9cf85a5684a
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Modifications to timer drivers and interrupt setup, to manage
the tickless idle for the x86 architecture
Change-Id: Ie02d484b7e5636de6ea382ba2eeed57e704c8498
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Looking at the IDT in a debugger is confusing, add a pretty-printing
function.
Change-Id: Iacc5e204e5d11e3e875c75ddf6d2e2e80b230299
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It was, in a nutshell, wrong. Fortunately, the incorrectly
specified fields weren't being used by anything.
Change-Id: I0fa63fa16a267502744a7a2c82865c7de8b5446e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
DEBUG isn't tied to any config option. Just use assertions.
Most of the time return values aren't being checked anyway.
Change-Id: I7457dcf00e18505bd6bcd98d46288545c03b5fbc
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Having priority levels 0 and 1 reserved on x86 due to implementation
details on how the CPU uses the vector table is confusing to users,
and makes it unnecessarily difficult to share drivers between arches.
Now on x86, priority levels 0 and 1 are available. Semantically, all
priority levels have had 2 subtracted from them.
It is no longer necessary to specify a priority level when the
vector itself is specified. If an IDT entry has a specific vector
associated with it, any priority argument is simply ignored.
In gen_idt, some simplifications have been made:
- The printed representation of a generated entry now fits on one line
- Some checks being done in validate_priority() were redundant, as
generate_interrupt_vector_bitmap() also ensures that there are
sufficient free vectors within a priority level.
Change-Id: I26669d8ee0a53f48fbc2283490a8c42d8b1daf8e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The argument to _common_dynamic_exc_handler() in the C domain
was still being set up the Sys V way. Arguments are popped off the
stack in reverse order, so _ExcEnt pushes *pEsf for arg 2, and then
the stub pushes the stub_num for Arg 1.
For IAMCU case, *pEsf is placed in EAX which is where argument 1
lives; static exception handlers take just one argument. However
since we're calling _common_dynamic_exc_handler we also need to
supply the stub_id, which we put in EDX (where arg 2 goes).
Rather than swapping things around at runtime the prototype for
_common_dynamic_exc_handler() is adjusted to fit the calling
convention in use.
Change-Id: Id43cbc3b86d90f941cea771678b2796ae5f1358d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds logger support to iamcu core for the following features:
- context switch logger
- interrupt logger
- sleep logger
Change-Id: Icfbd5fa787633045ba2895e8c28b652c55575b86
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
The common stub code didn't prefix the arg to 'mov' with a
'$', causing the assembler to generate code which tries to
dereference the argument before sticking it in EAX.
Change-Id: I0e201f799565d9709e3969b82ae2eb3f93a78b3a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The ASM stub invoked by irq_offload() wasn't switching to the
interrupt stack.
Change-Id: I0c52092a50396aa892e71f0501bbda38395d7554
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Making pipe driver configuration for quark_se makes no sense for the
board. First it simply wrong since IRQs for serial are 5 and 6 and
when using PIPE care should be taken to allocate right way serial and
Bluetooth for the given UARTs.
Change-Id: I4cb3227a8be34fbfa089a457e6d9977e4adcfd19
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32 symbol must be editable through
configuration menus and configuration snippets (QA request).
Adding a title for the kconfig symbol makes it editable.
Change-Id: Id0147a50d94033e1392327935bcbfbdb5a9eedd8
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
This driver uses the QMSI library and mostly translates calls from the
Zephyr API to QMSI ones.
This driver conflicts with the native driver implemenation. In order to
enable it, you must set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="PATH_TO_QMSI"
CONFIG_SPI_QMSI=y
CONFIG_SPI_QMSI_PORT_0=y
CONFIG_SPI_QMSI_PORT_1=y
Missing:
- Support for using a GPIO pin as Chip Select;
Change-Id: I0d8eca88a2a803b6b3604f396f874313fe90753c
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Decisions on compiler optimizations were done on the architecture level,
this does not scale and some SoCs will have different optimization levels
or compiler options needed. Moving this to the SoC makes it easy to optimize
differently when using the same CPU which we use to set the right optimization
now on the architecture level.
For IAMCU platforms, use the right architecture and tuning.
-march=lakemont -mtune=lakemont -miamcu -msoft-float
Change-Id: I458afca5feb9be5de8dcae559d6dcac3c6d6a2a7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Due to an issue with the interrupt-based transfer API from QMSI driver,
the 'transfer' callback from the shim driver (i2c_qmsi_transfer) is
implemented with polling APIs. This is not ideal because we are not able
to sleep the current thread (so another task can be scheduled in) while
the i2c operation is carried out.
The interrupt issue with the QMSI driver has been solved then this patch
fixes the shim driver so it uses the interrupt-based API and adds extra
code to handle the thread synchronization.
Finally, this patch also moves all 'struct device' related definitions
from the bottom to the top of the i2c_qmsi.c file so the DEVICE_GET
macro can be used in transfer_complete() and removes the init.h include
since it is not needed anymore.
Change-Id: I7ef7ce4cea6fcc939e310e5fe12c406645f6a16e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
IRQAGENT3 is initialized explicitly, but IRQAGENT0 isn't and its value
is based on the value the BIOS or bootloader had set before. Fix this by
explicitly initializing IRQAGENT0, and swizzle the IRQs to reduce
conflicts.
Update the pci_pin2irq function to accommodate for these changes.
Also remove pci_irq2pin function since it is unused.
Change-Id: I7b1dfc7659ab227fe66711a3af5a1f34fd4a7972
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
To debug PCI drivers on QEMU, it may be desired to enable CONFIG_PCI for
QEMU targets. Since the PCI driver requires a SOC pin2irq translation
function, add such function to IA32's SOC header file.
Change-Id: Icf6f88aa14ae29d70fe12dc80a708e6a2e992ba8
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
We don't normally need a runtime-mutable GDT; make it optional to
activate a second copy in RAM. Regardless of whether it is in RAM
or ROM, it can be accessed by the '_gdt' symbol.
Change-Id: I5ce955f4b8875eb60040917ceaacc07d7e5941ac
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Move BLE configuration to board and enable GPIO for NBLE.
Change-Id: I99c309656430936edf6766fc99fe83b011801bb4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adds basic support for communication with Nordic BLE (NBLE) chip
connected to UART.
Change-Id: I3651e291ec18805a63ecd3d240dce62273e3c498
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Mostly SoC initialization and some kernel subsystems, but also some
device drivers like the interrupt controllers.
Change-Id: I8dc1844c33acd877c075b6b03558fdca6f87500b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().
Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.
Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Most systems have far less than 256 IRQ lines available, so
save some bytes in ROM by making this a config option.
On systems with MVIC, omit the table entirely as the mapping
is fixed.
The build cmd_gen_idt is slightly easier to read and will fail
immediately if any of the commands in the sequence error out.
Change-Id: I411f114557591e5cd96b618e6f79f97e8bedadf0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.
Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This bitfield is only needed to find unused vectors in the IDT
for installing dynamic interrupts.
Change-Id: I34ecd330774a0e50f240b4396527682eded29627
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fix an issue where, if a task is pending on a nano timeout, the duration
it wants to wait is not taken into account by the tickless idle code.
This could cause a system to wait forever, or to the limit of the timer
hardware (which is forever, for all intents and purposes).
This fix is to add one field in the nanokernel data structure for one
task to record the amount of ticks it will wait on a nano timeout. Only
one task has to be able to record this information, since, these waits
being looping busy waits, the task of highest priority is the only task
that can be actively waiting with a nano timeout. If a task of lower
priority was previously waiting, and a new task is now waiting, it means
that the wait of the original task has been interrupted, which will
cause said task to run the busy loop on the object again when it gets
scheduled, and the number of ticks it wants to wait has to be recomputed
and recorded again.
Change-Id: Ibcf0f288fc42d96897642cfee00ab7359716703f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Adds C++ support to the build system.
Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Introduce the GPIO QMSI-based implementation. This is basically a
shim layer that implement's Zephyr's GPIO APIs on top of QMSI drivers.
This is an alternative driver that conflicts with the previous
GPIO_DW implementation. In order to enable it you must set:
- CONFIG_GPIO=n
- CONFIG_GPIO_QMSI=y
- CONFIG_GPIO_0=y
- CONFIG_QMSI_DRIVERS=y
- CONFIG_QMSI_INTALL_PATH="PATH_TO_QMSI"
Note that this driver currently only supports one controller instance,
GPIO_0. It is implemented this way due to a limitation from the current
version of QMSI. QMSI versions later than 1.0 doesn't have this
limitation.
Missing:
- support multiple controller instances (gpio_0, gpio_1, etc);
- enable level triggered interrupts in sync with system clock,
through setting INT_CLOCK_SYNC properly.
Change-Id: Ib61b153dae9741806a9a31d7dc1f82b96d000fbe
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
It wasn't immediately clear in _execute_handler() that
enable_interrupts() didn't actually do anything if
CONFIG_NESTED_INTERRUPTS wasn't enabled.
If we are not using nested interrupts, perform small optimization
1) The call to disable interrupts isn't necessary as interrupts
are already disasbled
2) The check for !_nanokernel.nested in a couple places always
evaluates to true if nested interrupts aren't used
Change-Id: I7e66cee0466d03bc1172a572e19389accf6e0e62
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On Quark SE, SPI might require GPIO to be ready before hand, to emulate
CS, thus providing an option to tweak the intialization priority for SPI
DW driver.
Change-Id: Ifa373948ac8227bf6e4ed1113bcb4dc9139b6663
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Quarks SE owns a GPIO controller which is always on (so not clock-gated)
thus providing it base address, the pins it handles etc...
Change-Id: Ifceb7cb74e763a91130d615ba19756ddcbe97a23
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is valid only for Quark SE and Quark SE SS, where it requires to
unmask the interrupt for each specific controller. Thus making the
function generic, using the parameter as the specific mask base address.
Change-Id: Iea0a412b8d94a1ab5e1f3e339eaf632eacee5797
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The original value of 128 was selected more or less randomly, and
isn't sufficiently large enough for QA needs.
Change-Id: I8a9fcc86d6b5fa7dc5ba05896c62f7dd608f9ed2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This reverts commit 778d5b11c5327be4b40c7745e9beaecfd6327e13.
This patch has been identified as breaking the build when trying
to manually build non-x86 applications.
Change-Id: I1857745049dfef7193de58737108314b7aae01c5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This option misunderstands how XIP works. The IDT is ALWAYS in ROM,
the question is whether crt0 will copy it into RAM or not. You can't
save ROM space in this way.
Change-Id: I58025e3d71ead35730d0a5026213299b4fcb5eb9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are not (yet) used anywhere and generate unnecessary warnings.
Just remove them.
Change-Id: Ibae472c4a639466c221cdc354232780db04e963e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Define configuration for Nordic chip connected to UART0.
Change-Id: Ia6007def747932e5f9fbd57f1ea8005892a2f793
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Decisions on compiler optimizations were done on the architecture level,
this does not scale and some SoCs will have different optimization levels
or compiler options needed. Moving this to the SoC makes it easy to optimize
differently when using the same CPU which we use to set the right optimization
now on the architecture level.
For IAMCU platforms, use the right architecture and tuning.
-march=lakemont -mtune=lakemont -miamcu -msoft-float
Change-Id: I0f77cffe7a139f8b2620935094437d0dfd160dfe
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Kbuild system first looks for a Kbuild file, then it looks for
a make file.
Use the Kbuild for object building and leave the Makefile for definding
build options and compiler flags and other SoC related defines.
Change-Id: I0be59bb5ae02a29108a188efbd6f14dcdb7de4ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Currently, if we disable I2C_DW through 'menuconfig', I2C_DW_0* and
I2C_DW_1* options are not disabled even if they depend on I2C_DW
option. This makes the menuconfig confusing and we end up with the
wrong config set in .config file:
...
CONFIG_I2C_DW is not set
CONFIG_I2C_DW_0=y
...
CONFIG_I2C_DW_1=y
...
This patch fixes this issue by surrounding the I2C_DW_0* and I2C_DW_1*
options with 'if I2C_DW'.
Change-Id: I7e949b066425bca2533f8b84b9ea7b1915369ff0
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
On SysV ABI, the NANO_ESF parameter is passed in via the stack.
For IAMCU, this is instead expected to be in EAX.
_ExcEnter is currently using EAX to stash the return address of
the calling stub while it does a stack switch. Change it to use ECX
for this purpose, and if we are running with IAMCU place the
parameter in EAX instead of pushing it.
The output of the fault handler has been cleaned up a bit and it
now also includes the code segment.
Change-Id: I466e3990a26a1a82dd486f3d8af5395eab60b049
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was never implemented on ARC/ARM and has been superseded
by irq_offload().
Some checks that were only done with CONFIG_LOAPIC_DEBUG fall
under the category of 'shouldn't ever happen' and have been
converted into assertions, instead of propagating return values
which are largely never checked.
Change-Id: I4eedca05bb7b384c4f3aa41a4f037f221f4a9cfe
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch introduces the 'QMSI RTC device driver' which is simply a shim
driver based on RTC driver provided by QMSI BSP.
Some config options are independent of the driver implementation used,
so use a consistent name for them. In this case RTC Interrupt number and
Priority use the same config options for both the QMSI and DesignWare
drivers.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_RTC=y
CONFIG_RTC_QMSI=y
Change-Id: I48292406e5472e5786f3b9abbeb71016a273bfec
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
If we are not doing any dynamic interrupts or exceptions, we
can put the IDT in ROM and save a considerable amount of RAM,
up to 2K if the IDT is the default size of 256 entries.
The _interrupt_vectors_allocated table can also be put in ROM
if we're not using any dynamic interrupts.
We introduce a new Kconfig option to force the IDT to be in RAM
for situations where no dynamic IRQs are used, but ROM footprint
needs to be conserved.
Change-Id: I38c9f1a8837b4db9f3dea1caa008374a26cbbf1d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This enables building with the iamcu variant of the x86 compiler
and enabled using the IAMCU ABIs.
Change-Id: Idf71251898e250b8df73c065462c93c289879fe2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There are a few bits missing on enabling I2C controller on
quark_d2000_crb. This adds the missing bits.
Change-Id: I05bbe8367a9e69962db573d496f1f9f0167ba597
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch moves the CONFIG_STACK_CANARIES check from architecture's
Makefile to the root Makefile since this option is kernel-related,
not architecture-related. This way we avoid replicating the same
CONFIG_STACK_CANARIES check in several Makefiles.
This patch also removes some blank lines from the Makefiles it touches.
Change-Id: I458f92fa6799526c608369d1e56579936bcb196e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Changes the nanokernel stack API so that the timeout parameter must be
specified when invoking nano_isr_stack_pop(), nano_fiber_stack_pop(),
nano_task_stack_pop() and nano_stack_pop().
This obsoletes the following APIs:
nano_fiber_stack_pop_wait()
nano_task_stack_pop_wait()
nano_stack_pop_wait()
Note that even though the new API requires that the timeout parameter
be specified, there are currently only two acceptable values:
TICKS_NONE and TICKS_UNLIMITED
This nanokernel option does not support CONFIG_NANO_TIMEOUTS.
Change-Id: Ic7f16ee30c3534115ceffa19ef8591ecc5a79080
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel LIFO API so that the timeout parameter must be
specified when invoking nano_isr_lifo_get(), nano_fiber_lifo_get(),
nano_task_lifo_get() and nano_lifo_get().
This obsoletes the following APIs:
nano_fiber_lifo_get_wait()
nano_fiber_lifo_get_wait_timeout()
nano_task_lifo_get_wait()
nano_task_lifo_get_wait_timeout()
nano_lifo_get_wait()
nano_lifo_get_wait_timeout()
Change-Id: Ie9f93e46da42ea33c32544c02ab1d70b893cc198
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel semaphore API so that the timeout parameter must be
specified when invoking nano_isr_sem_take(), nano_fiber_sem_take(),
nano_task_sem_take() and nano_sem_take().
This obsoletes the following APIs:
nano_fiber_sem_take_wait()
nano_fiber_sem_take_wait_timeout()
nano_task_sem_take_wait()
nano_task_sem_take_wait_timeout()
nano_sem_take_wait()
nano_sem_take_wait_timeout()
Change-Id: If7a4bce1bd8ec8d6410d04f3c16ff1922ff0910e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel FIFO API so that the timeout parameter must be
specified when invoking nano_isr_fifo_get(), nano_fiber_fifo_get(),
nano_task_fifo_get() and nano_fifo_get().
This obsoletes the following APIs:
nano_fiber_fifo_get_wait()
nano_fiber_fifo_get_wait_timeout()
nano_task_fifo_get_wait()
nano_task_fifo_get_wait_timeout()
nano_fifo_get_wait()
nano_fifo_get_wait_timeout()
Change-Id: Icbd2909292f1ced0bad8a70a075478536a141ef2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The UART on Quark SE and D2000 supports fractional clock divider.
It is used to limit frequency error for supported baud rates.
Change-Id: I1f39a95db09f4a5a4116edc700a10e4b9ecfa2bd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is a generic Atom configuration that can be inherited by boards
with Atom SoC like the minnowboard.
Change-Id: I06ab999062be7811d14755fd34440dee8f8b81ed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
No need for the same SoC configuration with different names. Use IA32
as the "SoC" for qemu_x86 "boards".
Change-Id: Iee00538701c5ece14d0c3df637b0aaa54790f0e2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Using LOAPIC Timer as default since it is the default for most target
X86 systems.
Change-Id: I71c9b307839ebcf46fb28e1b709089de600af83f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We had one pinmux per platform with support for multiple boards.
This moves pinmuxing to boards as first step. Common functions that
are exposed by the API need to be moved to driver while keeping the
muxing configuration with the boards.
Change-Id: I2b4fabf663db98d644abcb5d51ba83adc6f74541
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Galileo pinmux configuration and reboot code belong into
the board and not the SoC.
Change-Id: If862178569438a8901902088bd085275416c25ef
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define boards based on platforms/SoCs and define them under boards/.
Also unify the naming of all platform, SoC and board files and use
platform.h for platforms and board.h for boards.
Change-Id: Icfeb96479ab5800aca98c80a79bdc3cecd645314
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Galileo board is based on the X1000 SoC, so move galileo to
boards and create this SoC instead, inheriting all SoC related code
and configuration items.
Change-Id: I9b39f1b44644775ee48acae284b82bae7876fffb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
According to the schematic, SPI1_M_ should be properly mapped out
on the pinmux. This should enable the SPI1_M functionality on the
Arduino / Genuino 101 board now.
Change-Id: Ided0147e7c2d835aa58fdc5860e7ca7f55d9e566
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Updating the pinmux to use a local static table for each pin select
option. Instead moving to a static series of function calls that
move the data from the RAM section to the ROM section.
This impacts only the Quark D2000 and the Quark SE chips. It does
not show any impact to the basic_minuteia tests.
All said we see small changes that amount to some values like:
test platform ram_%_change rom_%_change
======================== ============ ============ ============
microkernel:footprint-max quark_se-x86 -0.01 0.0
microkernel:footprint-reg quark_se-x86 -0.02 -0.01
microkernel:footprint-min quark_se-x86 -0.07 -0.02
nanokernel:footprint-max quark_se-x86 -0.02 -0.01
nanokernel:footprint-max quark_d2000 -0.01 -0.01
nanokernel:footprint-reg quark_se-x86 -0.03 -0.01
nanokernel:footprint-reg quark_d2000 -0.02 -0.02
nanokernel:footprint-min quark_se-x86 0.04 0.01
nanokernel:footprint-min quark_d2000 -0.07 -0.04
Change-Id: Ib69403eced60a8c784887dca9dd1954ce73a3e70
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Currently the Quark SE and Quark D2000 platform are only included
through the use of a compile fence one level higher in the Makefile.
Adding in a secondary compile fence to ensure if that check ever
changes, we won't be in trouble.
Change-Id: I5e39faffb4289f80901c0264a50a3e770db3388a
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Initial import of the pinmux configuration for the Quark_D2000 series
boards. Some minor tweaking of default values may be needed depending
upon expected usage scenarios.
Change-Id: I3b22219546a6534c7c695d0917a35f6f46b03cf1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adding support for the pinmux pins to set the pullup and input enable
registers. On the Arduino_101 board some pullup pins specifically can
be used to cause a reset for the Arduino sketch being run. Its use on
other pins is currently being investigated.
Change-Id: Id3293a4da84ea5bf553bf62ccb12782cb88503a5
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Naming convention should follow the IP_noun_verb concept. In this case,
renaming several functions from (for example) pinmux_set_pin to
pinmux_pin_set, while also correctly naming the function to their
specific tasks.
This is being done to make way for the ability to change the input
value, pullup value, and the slew as well.
Change-Id: Iec6f1723a48f80b66f3cea44df9bb6925972f6af
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Extending the public interface of the pinmux to allow the end user
to set a pin as an input/output and to pull up the value on
a specified pin.
Change-Id: Ie0a3b6432dd8c7d7a02f32e3d22049bdd99f1410
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Allow usage of alternative drivers and do not hardcode drivers
to zephyr own implementation.
Change-Id: Ieb55b5dc88b3643f276b7c48facef7f1c1c42fa7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The LCD display is an add-on, not a feature of the platform or the
board.
Set the defaults and remove the definition from Galileo Kconfig.
Change-Id: Ic319cd765d2dc1fe08cc65615680821fe9bc6a83
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The pin mux for Galileo Gen2 isn't set properly to enable UART0_RXD input from
the Arduino headers. EXP1's pin0 OE_N needs to be set HIGH to make the IO0
buffer an Input.
Change-Id: I0167f11ff5ee87bd5afe17300807b1aa4ed17abf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: David Antler <david.a.antler@intel.com>
The argument to 'lidt' is a chunk of memory with the base address
and limit of the IDT, and not the IDT itself. Horrible things
were happening when the IDT itself was being passed to this
instruction.
To be extra safe, disable interrupts while we modify the table
and subsequently reload it.
Change-Id: I9bf96f13a5f6e1be80d11bbfb9db3df1f2ed613a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add support for compilers conforming to the IAMCU calling convention
as documented by
https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf
Change-Id: I6fd9d5bede0538b2049772e3850a5940c5dd911e
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
All of these stubs at the end pop the stack and tell the LOAPIC
that we are at EOI. Put this in common code which falls through to
_IntExit(). Saves 8 bytes per static IRQ stub. There is also small
constant savings in the common code for dynamic IRQs.
Change-Id: If17e9f105928a4251a2cb3fc0d192649c1c4d84b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Quark SE Lakemont core has a hardware bug where the LOAPIC does
not properly notify the IOAPIC to clear the IRR bit for level-
triggered interrupts.
This patch introduces a workaround where the vector ID of the
in-service interrupt is manually written to the IOAPIC_EOI
register, resulting in the bit being cleared.
Unfortunately, in the context where EOI happens it's very difficult
to identify which IRQ line is being serviced, so this is done
unconditionally for all interrupts vectors whether they are registered
in the IOAPIC RTE table or not.
Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of having two config options to specify interrupt triggering
conditions, merge them into one option and clarify. This is now
similar to other drivers which have interrupt triggers.
Change-Id: I4e60c8c45a08d005dcc8256cb89e4c5be7c94307
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: I89090181acb5f48dd797e7773ab65c5f3d46c42a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: Ie7262b69226ebffa7e1b9e35725fda24b3fe089f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: I2d50457a45fae62ff085f7239712d580243253bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: Ia0a069464392714f38037841de52e8d265fa4f49
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The APIC by default uses vector 0xFF for the spurious interrupt
vector as described in the x86 CPU manual volume 3 section 10.9.
Make this its own config option defaulting to 32.
MVIC doesn't have a spurious interrupt vector, and due to the
fixed IRQ-to-vector mapping for this controller, continue
to use the last available entry.
Change-Id: I29bd09df700629dc0d15b30a6ae590b0df1ef890
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was only needed for an older implementation of software interrupts,
now superseded by the irq_offload() API (which doesn't interact with
the interrupt controller at all)
Change-Id: I8aa696d370ae1799872f6d70de69f3cb5b47456a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
To many people, IPI connotes inter-processor interrupts on SMP
systems. Rename this to IPM, or Inter-Processor Mailboxes.
Change-Id: I032815e23c69a8297c0a43992132441c240fb71e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
define CONFIG_PLATFORM only once in arch/Kconfig and set it
for every platform.
Change-Id: I8554bb36d2d15c3ee71fa63dfc3a763ebca956ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
excecptions are handled the same for i386_sysV_abi and iamcu calling
conventions ATM since we do not have any exceptions that we can
recover from there is no reason to have seperate implementations.
Change-Id: Ica8b332d7756a91b56f7080ac74771ad25d32753
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Add null definitions for the interrupt latency measurement API so we
can remove compile fences in C code.
Change-Id: If86eedf79afcb49002108814dd4fb864956eb667
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
functions defined in header files needs to be 'static inline' to
avoid linker issues if they are used more than once.
Change-Id: I2feb3560bde7cbc9a5c7932eca585be8036f3b25
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Other internal functions are shown in this header, no reason to
keep this a secret.
Change-Id: Icb7d36206148c281f1960d1ac10368d9bb3033f1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
According to the datasheet, there is some caching going on as a
performance optimization and the IDT needs to be re-loaded if any
changes are made at runtime.
Change-Id: I23864e1109907512066a9f8f3a36e3f719b9174b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Those empty C files are there because the current Kbuild
requires Makefile to be present at those directories,
(due to arch/x86/Kbuild), which requires building some object
files. So the empty source files are there to produce empty
object files to satisfy this.
Change-Id: I14056347ea14cff227d9e8960192e8673c0019b8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Change-Id: I1d379068f64855d5d4595838040ec50f97f638a0
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Change-Id: I1af8b2888779b2b58367feaff9ee1a6d97b4873c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Fix compilation errors due to variable ordering.
() Fix the default config for Quark/SE SS as
the kconfig options were renamed in previous
patches.
Change-Id: I1004ae332fb857b60ed90df59831e7bd9c490cb8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Saves an errno per-thread, retrieved via _get_errno(), instead of
changing the value of a global variable during context switches to avoid
a hit to the context switch performance.
Per-arch asm implementations are provided for maximum performance.
Enabled by default, but can be disabled via the CONFIG_ERRNO option.
Change-Id: I81d57a2e318c94c68eee913ae0d4ca3a3609c7a4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
() The SCSS has some additional registers to mask interrupts
from peripherals. This patch unmasks the interrupts for
the two UARTs on board, so that interrupts can be delivered.
() The UART interrupts are edge-triggerd, so set the config
options accordingly.
Change-Id: I39a1edccd830a8a19288982efa2e9d0faaaff8ba
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Clock gating is platform specific and not mandatory. Thus making it
Kconfig based as well as generic.
Change-Id: I4ea10eadb077ac3d57c9337b43b1a9fb14763302
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Clock gating is platform specific and not mandatory. Thus making in
Kconfig based as well as generic.
Change-Id: I01b7831536efd87cc66a95060fcf1faf4a340073
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Let's apply the interruption unmasking if only the mask is defined.
Which definition should be done in board.h thus applying the change to
quark_se and quark_d2000 platforms
Change-Id: I9c273e2e7e33dd077a54e8f9205fa949a5e3707a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Let's apply the interruption unmasking if only the mask is defined.
Which definition should be done in board.h thus applying the change to
quark_se and quark_d2000 platforms
Change-Id: Ie0a4912f0dfbd97f2273efed963f7810a985c0bd
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Base address, IRQ, interrupt priority as well as the instance name: all
are now Kconfig based. Thus Applying the change to quark_se and
quark_d2000 platforms. Sample code is updated as well.
Change-Id: I1c225c1b68d94b22ca10423b50a78a0ba09a27a5
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Base address, IRQ, interrupt priority as well as the instance name: all
are now Kconfig based. Thus Applying the change to quark_se and
quark_d2000 platforms. Sample code is updated as well.
Change-Id: Idcc89e6e9f4acc337fafc7d42f8de3061a5ece04
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Removed old style file description and documnetation and apply
doxygen synatx.
Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch remove the dependency of the ADVANCE_POWER_MANAGEMENT
for profiling sleep events that was supported only for microkernel.
Allowing us to also use this feature in nanokernel-only systems.
Change-Id: I1761eb6c4d72f477b419dfca5dc152b0fb69ee27
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
Set correct interrupt flags which are used with the console
handler.
Change-Id: I6a3a76826cedd0b4116f622701f2cb1161dd8adc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Set correct interrupt flags which are used with the console
handler.
Change-Id: I473a1fca6234ffb8d926457e8ccecfa29d1be6a5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Set correct interrupt values for this platform.
Change-Id: I97361b4420630e73bb8c8f812c943ee972cb8762
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removes the 'priority' parameter from the IRQ_CONFIG macro.
This parameter was not used anymore in any architecture.
The priority is handled in the IRQ_CONNECT macro.
The documentation is updated as well.
Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Although it contains functions called from ASM-land, there's no
calling-convention specific code here.
Change-Id: I3d912bdf28e6f3e797e6a2d6b745302b4c884b4a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The content of include/drivers/hpet.h is really private to
the driver and does not need to be exposed in public include
directory. So move the content into driver code.
Change-Id: Ica442e43c480a6b079b8d3c4e75e67adcfd0ba6b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Setting up new platforms to handle emulation, and make them the only
ones able to run on QEMU from the Makefile "qemu" target to avoid
confusion with other platforms. We have now platform qemu_x86 and
platform qemu_cortex_m3, also modification to the sanity checks to have
qemu support only on those platforms
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Change-Id: I9291918a1d58fea4f37750ada78234628f9a5d98
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Since all the necessary bits utilizing UART by index have moved to
use device name instead, the uart_devs[] can finally be removed.
Change-Id: Idbae6b46c0af9eef6c22c59e121e9d6a6b52426a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use device name to find the UART device for uart_pipe usage,
instead of relying on an arbitrary index.
Change-Id: I36aaa4ed8f0b4905e4e741ca1464947e59f30869
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use device name to find the UART device for Bluetooth usage,
instead of relying on an arbitrary index.
The default device names being used are derived from the original
board.h for each platform. Some of them point to the same device
as UART console. Since this is a Kconfig option, the default
can be overridden so this is not a serious issue.
Change-Id: Ibe82f3968e72ba60f9c033aa3dfcb2fb3c41dc75
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use device name to find the UART device for console usage, instead of
relying on an arbitrary index.
Change-Id: Iebe01c9bf392dfee6d8284367f67647f7d47561a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove the call to uart_init(), and let the UART drivers take care of
the port initialization.
Change-Id: Id3e46135ab993cb6596b1fb5339ab1664c65ab40
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove the call to uart_init(), and let the UART drivers take care of
the port initialization.
Change-Id: Ibeca65b3fe64feb7a203a793c01c525ff5e6afda
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Renames ns16550.c to uart_ns16550.c. This is to follow
the driver naming convention.
() Renames functions ns16550_uart_*() to uart_ns16550_*(),
following driver naming convention.
() UART ports initialization is moved into the driver itself.
All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
in each platform's board.h anymore.
() Renames CONFIG_NS16550_* to CONFIG_UART_NS16550_*
() Disable NS16550 for ARC as no port is defined anyway.
Change-Id: I76bbe25b9bc75eb62df81e533f84f4f63a5257b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IRQ line used for MVIC timer interrupts is 0, not 10.
Change-Id: I076bf9c8902e7384e493945e6689fcbefff59cad
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is currently valid for quark_se platform. It's used internally to
suspend and/or resume the gpio controller.
Change-Id: I5147568ba6b0450363566b5f9fd2e8aa7e41df49
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Change-Id: Ie58e8611a8fe9edec9ebcb123532a97f396098f4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no secondary GPIO controller on such SoC. Plus, the unique
controller controls at least 28 pins (if not 32, so I set 32), as
verified on boards.
Change-Id: I61c563671a908551250faa2a0fb9f9e2e17018d3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Simplify driver by using sys_io functions and implement
wdt_read_config
Change-Id: I119615f1c391daae43a3b8db30319c51167ae05b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Software interrupts or system calls aren't really appropriate for
zephyr, but we have an ongoing need in our test code to run a
function with arguments synchronously in interrupt context.
This patch introduces irq_offload() which allows us to do this without
separate initialization or having to manage fake IRQs in the
interrupt controller.
ARM assembly code contributed by Benjamin Walsh
<benjamin.walsh@windriver.com>
ARC is not yet implemented but will be in a subsequent patch.
irq_test_common.h has been removed and all test cases updated to
use the new API.
Change-Id: I9af99ed31b62bc7eb340e32cf65e3d11354d1ec7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Put initialization priorities as device driver Kconfig
parameter.
Initialization priority value for each platform is defined
in the platform Kconfig file.
Drivers and platform code use SYS_DEFINE_DEVICE to add
and initialization function.
Change-Id: I2f4f3c7370dac02408a1b50a0a1bade8b427a282
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Avoid having to remove quotes wherever the platform name is used
by exporting the variable only once.
Change-Id: I4cb51901e4ac19d70d0310fe6bbacd157f586661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add comment regarding the use of GAS when using clang, and remove
duplication of setting -Wa,--divide, which is needed for all toolchains.
Change-Id: Iab7257b038d1f4142c37a6c6c5979ef28f78a655
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Move the files that *know* about the calling convention in use by the
compiler. The routines exposed by the files moved to the i386_sysV_abi
directory follow the C calling convention specified by the
i386_sysV_abi which is the default for GCC. The upstream GCC has been
enhanced to support the iamcu_ABI that is optimized for processors
that implement the IA MCU instruction set. This new ABI provides code,
data and stack size improvements on IA MCU based systems.
This change is the first step in adding support for the IA MCU
optimized toolchains to Zephyr OS
Change-Id: I13bffee8007fb3f82aa31389b2c241065e8e315d
Original-work-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
When building for a certain platform, we have no idea
what architecture we are building for.
We used to specify the architecture alongside the board or platform
name and this was used to find the defconfig in arch/<arch>/configs.
By putting all board configurations we support in one place we do
not have to specify the architecture, just the configuration name.
Change-Id: Ib7e9f63b9a8051714dc207f583fd26ef620497d8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not depend on host architecture and use architecture definition
from the defconfig file of the board.
Change-Id: Idb3dd42524f26bd167a34d6eb024d4d9816e9730
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not depend on environment variables and use a kconfig variable
for defining the architecture.
In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.
Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not reference every platform, instead use the platform
name to tell make what to build.
Change-Id: I7498da7cdcdada754466222902f59fe4c6487d89
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move platform related data and definition to the platform
directory and include it using:
arch/<arch>/platforms/*/Kconfig.platform
This way we will able to add a platform as a directory of
content without the need to change and Kconfig files.
Platforms can then be included by reference (using repo or
git submodules and does not need to be part of the zephyr
project)
Change-Id: I5e71f5394c22edb346f7d61d9448b8e1c68e1f9b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Provide the proper irq for i2c, gpio and spi. And make relevant drivers
getting enabled easily once their domain is selected.
Change-Id: Ib8a428e11b6163a1b370b23baa34ea2fab733565
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Without that, it won't built when enabling support for dw i2c in
quark_se-x86.
Change-Id: Icce26488d870c273516dc9f34555176122bcb9c8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Build the actual driver when relevant
- Provide the IOAPIC stub
- Provide the IRQ flags for IRQ_CONNECT_STATIC
- Set the default IRQ priorities
Change-Id: Iea20ef67c92cf7f48791fba5a8021448b7059950
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Original name was too generic and confusing. This patch renames
driver to pipe UART and moves it to console drivers folder. Kconfig
destription is also improved.
Change-Id: I716fdbf7d636bbdc03b0fce27a59fd866f473246
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
The Intel Quark microcontroller D2000, is a low power, battery-operated,
32-bit microcontroller. Within its small footprint, the Intel Quark
microcontroller D2000 includes an Intel Quark ultra-low-power core
running at 32 MHz, with 32k integrated flash and 8k OTP SRAM.
Change-Id: I6ba121996edb0b5fbe596bd6ef3d6e3979ff73e9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This module is based on the standard Local APIC and IO APIC source modules.
This modules combines these modules into one source module that exports the
same APIs defined by the Local APIC and IO APIC header modules. These
routine have been adapted for the Quark D2000 Interrupt Controller which has
a cutdown implementation of the Local APIC & IO APIC register sets.
Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This cause problems with some configurations using hex.
Change-Id: I680c40d46e1fdf3da714f6412c8dda0e1ebb44f9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Keep things consistent across all platforms and make this
configurable and avoid hardcoding in linker.cmd file.
Change-Id: Iddeb5107854139249fda70378e07b83066d8a7a1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The driver should handle the initialization instead of relying on
platform initialization. This is to conform to the driver model.
Change-Id: Idc95d59bce2470b5118e416ee05f07548991a15c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When PCI bus is not enumerated, I/O memory and IRQ
numbers need to be statically initialized.
Change-Id: I4efcccd95d8048910f6c900c8daf46cbe3a5fa00
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Not supported in LLVM/clang. As it turns out,
this new implementation is 4 bytes shorter than its
predecessor.
Change-Id: I1f63b7a245dafcfc5a6dadc293875f00d02b997c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fix a few spots where building with with clang fails.
Change-Id: I621c7cb8daf119bf89ad512168d70e1c9b67e53f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clang support already existed in the Makefiles but was not complete
and some gcc options did not work with clang. Move those to be conditional
on the compiler used to make clang work.
To build with clang for x86:
make CC=clang -C samples/microkernel/apps/hello_world/
You still need the gcc cross environment for various tools.
For now, only x86 was tested.
Change-Id: Ic5aeab4f80d312e1d1312a4a9fc885a43f760270
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.
The change in API means that device drivers and sample
applications need to use the new API.
IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()
Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Such controller offers 2 blocks (respectivelly Core Well and Resume
Well) on Quark x1000, with 2 and 6 GPIO pins to use.
Change-Id: I50075f0880bef4574e9eeb1c65602082e8da647a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
We already had this kconfig defined as hex for arc. Make it
readable and change the variable to hex to comply with what
we had already.
Change-Id: Ib8bc72f27d1b97ba2c886201ec29fb13aa4fa429
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We're smart, we can look up the vector IDs in a book if we
don't already know what they are.
Change-Id: Iaff3986d7c96dea597be4b2a5b13721ab57980fa
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Unused, uses IRQ17, which conflicts with UART1.
Change-Id: I5d285ee8a2e7e5d45b38a85a417bd36f0e4bb92e
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
As the system always operates in ring 0, neither the SS nor ESP registers
are pushed onto the stack when an exception or an interrupt occurs.
However, as the ESP field is still relevant to debugging fatal errors, a
place has been carved for it in the NANO_ESF.
Change-Id: Ibb2578c69fa6365fd6e9dbf7b51f461063dadc68
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
As page fault exceptions can not occur in the system as it is currently
designed, there is no need to track the CR2 register as part of the
exception stack frame.
Change-Id: I75d7a74c5d2c6efcc0e9141d2662861bc2052629
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The -no-reboot flag causes QEMU to exit when trying to reboot through
the RST_CNT register.
Change-Id: I01262753587d2fc4e787262a8368ddba39fdeaa1
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Implementation of the sys_arch_reboot() call for galileo, using the
RST_CNT register (I/O port 0xcf9).
Change-Id: I00fbf4aaaf746f640674da6880e1d6c5aa230e06
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
CONFIG_RAM_SIZE
CONFIG_ROM_SIZE
Available to x86 based platform configurations.
Change-Id: I3dda770a9063e3c717023b1a83761f32caa2c590
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Eliminates issues with compilers that have different C calling
conventions.
Change-Id: I9318edd5eea6b6bacdf3da2c28e0e29315d5cdf5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Eliminates issues with compilers that expect different C
calling conventions.
Change-Id: Ic70a15926380671a7b9c058b53400b10b5c870a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This doesn't make any assumptions on calling conventions or
the structure of the stack, and should thus be portable to
compilers that implement different C calling conventions.
In order for the rewritten functions to take up the same code
size as the pure-asm counterparts, -fomit-frame-pointer has
been specified for each of them, otherwise an extra 4 bytes
is used for every function.
The generated assembly code by these new functions has been
verified in GDB to be the same as the old ones, except a few
trivial things like particular registers used.
Change-Id: I9a896cbfc3e7f4c2497d749140729d28b32f1c9d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was only needed on legacy platforms which are no longer
supported.
Change-Id: I4a3312f3698c4fc8bbf0df4610af7b69a9056f80
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This had bit-rotted to the point where it was breaking the build
and was only needed on legacy platforms that are no longer
supported.
Change-Id: I4fcfc38bacac58761fba475701e0c27d7b8b7a27
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This option is not building and currently not supported, removing
it because there does not seem to be a use case for it.
Change-Id: Idb8ffedf83f43cffc68a01573c6f2d1a90fc40fb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This reverts commit 58fd0778c6dcc6bd3148b5d07615cd7bd777f456.
Change-Id: Ibffe036d2e182652b3c966c10ed405c9386f823c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.
Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.
CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.
Some other out-of-date verbiage in comments related to supporting
non-APIC removed.
Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.
SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.
All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.
_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.
Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Clang support already existed in the Makefiles but was not complete
and some gcc options did not work with clang. Move those to be conditional
on the compiler used to make clang work.
To build with clang for x86:
make CC=clang -C samples/microkernel/apps/hello_world/
You still need the gcc cross environment for various tools.
For now, only x86 was tested.
Change-Id: I1a50c3a82d79ff3001beb4366961ca810eeb6006
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to have a name according to the functionality of the feature.
This commit rename any text, function and variable related with the
Profiler name to Event logger.
Change-Id: I4f612cbc7c37965c35a64f06cc3ce5e3249d90e5
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
Detect the presence of CLFLUSH instruction and cache line size at
runtime. It is still possible to set them manually via kconfig options
if the values are known.
Change-Id: I00bda1de4c5c241826ead6f43b887b99a963cc7b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Removing many of the typedefs that are only used once to lessen the
checkpatch warning about creating new typedefs. A handful have been
behind as they would require a more invasive change to the code. It
has yet to be determined if this is a worthwhile endavour.
Change-Id: Ibeb29e0a1d37e8121218fccf0d986cbebd226e85
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Provide a preconfigured base address for MMIO and a preconfigured IRQ
pin identifier for the first PCI Ethernet MAC in the Intel Quark X1000
SoC.
Change-Id: I1b527df6c3b1b65da9f0233464e54157029f04f5
Signed-off-by: Michael LeMay <michael.lemay@intel.com>
Change-Id: I099773701448b09bc3fa0607552fadec39e24407
Work-by: Jeff Blais <jeffrey.blais@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Signed-off-by: Jeff Blais <jblais@windriver.com>
If PWM had been configured by some other application after the last
power cycle, it would appear to work fine. However, an application using
PWM loaded right after a power cycle would not work, since the configure
call was missing during boot.
Change-Id: I389ca2122e1a4a7ea6d298efb327438761336d75
Work-by: Mike Hirst <michael.hirst@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Streamlines the prompts and help text for the floating point
configuration options to make them easier to understand. Also
fixes a help text error that said fibers using the floating point
registers needed to provide additional stack space, which is
incorrect.
Change-Id: Ib6fc13460999ec7f737118728a363b4e10d23fcf
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
galileo.c currently calls itself system.c in a comment. It lies.
ia32.c currently calls itself system.c in a comment. Don't believe it.
ia32_pci.c currently calls itself system.c in a comment. It lies.
Change-Id: Icdba074ff2e2e478529bc5757c90b5adbc9dcb8a
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
GPIO7 and SPI1_MISO share the same muxer and SPI1_MISO is an input pin.
Change-Id: Ib55e03680fadc3f8ce2725fad6761b3551134081
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The \NOMANUAL tag is a remnant from days of yore and is no longer
needed or useful. Cleaning up the code references to this.
Change-Id: I1b8cc9c9560d1dbb711f05fa63fd23386789875c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This was only needed for the older 8259A style PICs which are no
longer supported.
Since we now just support APIC, we always just call loapic_eoi which
no longer requires an argument and informs the IOAPIC that the interrupt
is complete if necessary.
Change-Id: I15c9b7b4f03b872656220af32220b62e043bfa6b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
SPI port 1 needs the pinmuxer to be initialized first. Or then, all
modifications required from the CS GPIO logic won't apply.
Change-Id: Ibe4b2d4096065a9add23373075090d5e8a014650
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
As for the SPI port 0, SPI port 1 needs a GPIO pin to emulate the CS.
Change-Id: I00911cd25c3fa0ae17a02ee6f43cbea7f4fbcca2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
ioapic_irq_set() needs a vector number: all calls to it now use the
_IRQ_TO_INTERRUPT_VECTOR() macro as expected.
The previous change by which interrupt priorities are now honoured
correctly when connecting ISRs to IRQs statically also changed the way
the interrupt vectors are assigned.
Instead of computing them like this:
interrupt vector ID = IRQ + INT_VEC_IRQ0
They are now determined by a macro:
interrupt vector ID = _IRQ_TO_INTERRUPT_VECTOR(irq)
Change-Id: Icc4576ac9bc6891c8662bcc17a543333eb8745e0
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Updates the 'gen_idt' tool to generate a mapping of IRQ numbers to
interrupt vector IDs, thereby allowing the IRQ priority to be utilized
when statically connecting an interrupt.
Change-Id: I2e54ceb65145682820dfbd8ca1ee6ec68d71ce1a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the default IRQ priority level from 0 to 2 for the following
kernel configuration options as priorities 0 and 1 are reserved for the
first 32 IDT entries.
SHARED_IRQ_0_PRI
SHARED_IRQ_1_PRI
I2C_DW_0_INT_PRIORITY
GPIO_DW_0_PRI
GPIO_DW_1_PRI
SPI_INTEL_PORT_0_PRI
SPI_INTEL_PORT_1_PRI
Change-Id: I0fc821c68156eb1e1fe776b2bd4ff5890bba40e8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The Kconfig option NUM_GDT_SPARE_ENTRIES is no longer relevant.
Change-Id: Ie41ed3bef50bd4198c4cee45e160f008c53bfed4
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Renames the Kconfig option NO_NESTED_INTERRUPTS to NESTED_INTERRUPTS
as it is typically easier to follow positive logic than it is to
follow negative logic.
Change-Id: I68f9220621545a72254ba561aa3cb488e59e402a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
CONSOLE_HANDLER depends on UART_CONSOLE so this define is not needed.
Also mark parameter unused.
Change-Id: I58b52955a22de3fb3216454a1d802eef63c9f845
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Configure IOAPIC for Bluetooth interrupts connected to UART.
Change-Id: Iad58f52e95c05245d38dd0f4cb10494b53bad8e0
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Configure IOAPIC for Bluetooth interrupts connected to UART.
Change-Id: Ia93f71a8e8435c523dd8ee232f9ce4cf9266b978
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Configure IOAPIC for Bluetooth interrupts connected to UART.
Change-Id: Ib9c208a1d396bb6f51531e970d515e42ff416e6c
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Change-Id: Ie051000e3d3f0f5bdc330d0265010c37acb873bd
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: Iff0d922a7b9ad498820527e71b31701bb06c400e
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I2276676142deea21cf8079449ce153f2fb887a8e
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I819d13f0d7a23e3a61dcda6a3ced18810b192158
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: Ie655181d5ed11a71cadfa218f396f0b64992ca34
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Moving many of the functions from the old format of inline comments to
the newer doxygen format.
Change-Id: Ib0fe0d8627d7cd90219385a3ab627da8f9637d98
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This workaround is no longer required.
Change-Id: I797237be77b7568fe836df0e82640027d8d4882b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Updates several files to remove mention of Diab toolchain
support, which is no longer supported. These changes do not
affect system operation.
Change-Id: If9de85e595f6685295e565bc94ca17f51d87513f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Daniel Leung