Moves the flash memory definitions from Kconfig to device tree for the
rv32m1 ri5cy and zero-riscy cores.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Moves the sram memory definitions from Kconfig to device tree for the
rv32m1 ri5cy and zero-riscy cores.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a new argument to the openocd runner to optionally specify the
config file. Updates the rv32m1_vega board to use different openocd
config files for the ri5cy and zero-riscy cores.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Introduces a new rv32m1_vega board configuration for the zero-riscy
core. It assumes that the soc has been reconfigured with openocd to boot
to the zero-riscy core instead of the ri5cy core.
Refactors the board-level device tree so the ri5cy and zero-riscy
configurations share common definitions for the led, button, and sensor
nodes.
Tested with:
- samples/hello_world
- samples/synchronization
- samples/basic/blinky
- samples/basic/button
- samples/sensor/fxos8700
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Same deal as in commit 4638652214 ("Kconfig: Use 'default' instead of
'def_bool' in Kconfig.defconfig files"), fixing new stuff that got
introduced since then.
Some symbols, like ALTERA_AVALON_PIO, are only defined in
Kconfig.defconfig files, and so need the def_bool.
Motivation (from the note at the end of
guides/kconfig/index.html#common-shorthands):
For a symbol defined in multiple locations (e.g., in a Kconfig.defconfig
file in Zephyr), it is best to only give the symbol type for the "base"
definition of the symbol, and to use 'default' (instead of 'def_<type>'
value) for the remaining definitions. That way, if the base definition
of the symbol is removed, the symbol ends up without a type, which
generates a warning that points to the other definitions. That makes the
extra definitions easier to discover and remove.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A new role :zephyr_file: is available that renders to a link to the file
or folder in GitHub. Find appropriate references using :file: and
convert to :zephyr_file: to take advantage of its linking capability.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
We expect that identifier in yaml will match board name for sanitycheck.
Change the identifier to match so sanitycheck runs propertly.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This fix allows Renode to resemble the time flow of the hardware more
precisely. The performance value was established manually, there is no
indication in the docs on what is the average performance.
It allows tests/posix/common/portability.posix to pass, but fails on
tests/kernel/lifo/lifo_usage/kernel.lifo.usage.
The latter also fails on hardware.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Remove most unnecessary instances of `export` and `cmake` use that can
instead be replaced with `zephyr-app-commands` or similar. This is to
avoid documentation using different mechanisms to describe the same
actions and in preparation for documenting `west build` everywhere.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Be consistent in how board docs are named and move all to index.rst.
This will make the URL to the board documentation predictable and easier
to remember.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Document the `west build` command in the section corresponding to the
west commands that deal with the CMake cache, which is now named
"Building, flashing and debugging" for consistency.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Enable the SPI driver on the HiFive 1
This makes the following configurations choices for the HiFive 1:
The SPI 0 peripheral driver is not enabled by default because it is in
charge of mapping the SPI flash into memory. This can be configured
using the CONFIG_SIFIVE_SPI_0_ROM KConfig option.
The SPI 1 peripheral driver is enabled by default and the pinmux is
configured for all of its outputs
The SPI 2 peripheral driver is enabled by default because it is present
in the DTS for the FE310, but because the QFN48 package used on the
HiFive 1 doesn't route those pins from the silicon die, the pinmux can't
enable the SPI 2 pins.
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This board directory supports the RV32M1 Vega board when targeting
a RISC-V CPU core on the main SoC.
Currently, only RI5CY support is provided via the rv32m1_vega_ri5cy
board name.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
The test suite will use the m2gl025_miv.resc Renode script to load the
platform.
Signed-off-by: Dawid Wojciechowski <dwojciechowski@internships.antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Removed Console dependencies from shell uart backend.
Generated define: CONFIG_UART_SHELL_ON_DEV_NAME for each board.
Fixes#10191
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
This board can run in recent qemu versions (>3.0.0), so enable it
instead of a dedicated qemu board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update the uart_miv driver to get params like name, addr, baud-rate,
clock freq from DTS generated defines. Fixup related board and soc code
as needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add minimal DTS support for the m2gl025_miv. The dts just has the core,
SoC, PLIC, and UART described. We still get memory related info from
Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove some references <board.h> that aren't need or replace them with
<soc.h> where that is the proper include to pull in. Also use "board.h"
instead of <board.h> for how we include the file when its local to the
board code itself.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The dts.fixup for the hifive1 board was not board specific but related
to the SoC. Move the dts.fixup into the SoC dir so any other boards
using this same SoC will take advantage of it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move to getting the clock frequency of the uart from the device tree
instead of a define in the board file. Cleaned up hifive1 board code to
reflect this change in addition to the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add the needed bits to get device tree support for the GPIO controller
on the Zedboard-Pulpino. This will allow us to move LED & button info
into the board.dts.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add simple device tree support for the Pulpino SoC and Zedboard-Pulpino
board port. This gets the UART info from device tree instead of soc.h
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We get several warnings of the form:
Warning (alias_paths): /aliases: aliases property name
must include only lowercase and '-'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rename GPIO_INT_CONF to GPIO_FLAGS in order to be able to use
the definition generated by the devicetree, eliminating the need
for definition in the board.h file
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
FE310 is the name of one SoC out of a range of products in the SiFive
Freedom line. The FE310 SoC port in Zephyr is compatible with all of
these products, so rename the SoC to SiFive Freedom
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Add first set of boards which can be built with xtools, this will
include all boards at some point, so we might need a better way to
whitelist toolchains that does not include changing every single board
definition file. For now enabling those needed for testing the new
toolchain.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds support for Microsemi Mi-V RISC-V softcore CPU
running on the M2GL025 IGLOO2 FPGA development board.
signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit moves code from fe310 platform into RISC-V privilege common
folder. This way the code can be reused by other platforms in future.
signed-off-by: Karol Gugala <kgugala@antmicro.com>
Both variables were used (with the same value) interchangeably
throughout CMake files and per the discussion in GH issue,
ZEPHYR_BASE is preferred.
Also add a comment with explanation of one vs. the other.
Tested by building hello_world for several boards ensuring no errors.
Fixes#7173.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Maureen Helm