Header files under arch/xtensa/include are considered internal
to architecture. There is really no need for two places to
house architecture internal header files.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
... from xtensa_asm2.c. Other architectures have
z_irq_spurious() and *_irq_is_enabled() test in irq_manage.c.
So follow the trend here.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
... from xtensa_asm2.c.
Everything has been stuffed inside xtensa_asm2.c where
they are all mangled together. So extract thread related
stuff into its own file.
Note that arch_float_*() may not be thread related but
most other architectures put them into thread.c. So we
also do it here.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_spin_relax() does not really fit into the scheme of
xtensa_asm2.c as it is mainly about handling interrupts
and exceptions. So move it into smp.c, similar to other
architectures which arch_spin_relax() defined.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simply to provide some consistencies on file naming under
arch/xtensa.
These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
xtensa-asm2.h only contains the function declaration of
xtensa_init_stack() which is only used in one file. So
make the actual implementation a static function in that
file. Also there is really no need to expose stack init
function as arch public API. So remove xtensa-asm2.h.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
* Wording on CONFIG_SIMULATOR_XTENSA
* Remove "default n" as default is no anyway.
* Remove some tabs as we almost never indent inside a if block
in Zephyr.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no in-tree user. Also, it is misleading as we use
SCOMPARE1 for spinlock too, not just IPC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should be defined at the SoC
or the board level since Xtensa cores are high configurable.
The default is just for ISS (Instruction Set Simulator). So
remove it from the arch level.
The xt-sim board is the only one in tree that is targeting
the ISS, so add it there.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is supposed to stress the host buffer and metadata handling.
It is not really testing any particular thing, ie. the pass criteria is
just that each peripheral can send and receive a fixed number of GATT
notifications without any device crashing or locking up.
Original version by Ahmed Moheib (from cloud2ground).
Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
We follow the path of the header to define the guard, aarch32 was
removed some time ago and the guards still had AARCH32 in them, just
remove it and keep the guard consistent and short.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The `az3166_iotdevkit` board doesn't have its RTC node enabled,
and is failing the following test:
`tests/benchmarks/footprints/benchmark.kernel.footprints.pm`
Enabled RTC node for that platform.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The `96b_aerocore2` board doesn't have its RTC node enabled,
and is failing the following test:
`tests/benchmarks/footprints/benchmark.kernel.footprints.pm`
Enabled RTC node and lsi clock source for that platform.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix misplaced in,out in @param. If any parameters are output,
mark the others as input for clarity.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
z_free_page_count is only used in one file, so there is
no need to expose it, even to other part of kernel.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
How cache test could be ran without CONFIG_CACHE_MANAGEMENT?
Adding qemu_x86/x86_64 as cache related API in x86 has proven to be
very brittle against changes recently: no test was at least verifying
it builds properly, not to mention running it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Without this, cache manipulation cannot work in x86.
clflush was introduced with SSE2 extension, but may be implemented
without this extension and it seems that qemu made this choice a
adding sse2 CPU capability does not include clflush. It enabled by
default in 64 bits, so let's take care of this capability only for
the 32bits version of the board.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Instruction cache related functions (see include/zephyr/arch/cache.h)
are not implemented in x86, thus let's not set CONFIG_CPU_HAS_ICACHE
which may end up in build failure if one sets CONFIG_ICACHE.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It did not build in x86_64 due to the fact that cr0 is a 64bits
register in such architecture, instead of being a 32bits one originaly
so the place holder has to follow that size. Such place holder must be
initialized to 0 to make sure no upper 32 bits ends up set which would
conclude in a general protection error.
Operand size specifier (l, q ...) is useless as well in this context.
Clearing up the masks by using proper macros.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
() Moves the architecture specific timing measurement APIs
under the timing measurement APIs group.
() Add SoC and board specific API groups.
() Document each SoC and board specific API so the doc shows up
for them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds two APIs which allow for configuring the cellular
network configuration of a cellular network device. like
a cellular modem. The first allows for configuring which
access technology to use, and optionally, which bands to
use. The second allows for getting all supported access
technologies are supported, and which bands for each tech
are supported.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Enforce that the initial attestation partition has the required
initial attestation key provisioned.
If the initial attestation key (IAK) is not present during boot of
TF-M the system will panic during initialization.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Introduce Kconfig option in zephyr build system that reflects the TF-M
cmake config variable with the same default value for dummy provisioning
and have it satisfy the IAK present requirement.
This configuration is not suitable for production, and by having this
in zephyr configuration we can have this as part of the hardened
configuration check.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Adds a charge_enable handler to facilitate enabling and disabling
a charge cycle. This deprecates enabling and disable the charge
cycle via the CHARGER_PROP_STATUS property.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
Changed the tx/rx pins in pinctrl *.dtsi files to match the
evaluation board circuit diagram for UART1.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
Submit resume event after remote wakeup (resume) signalling is
initiated. Handle it same way as in the usb_dc_nrfx driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This adds the expect_bt_bap_stream_ops_released_called function that
takes an array of streams to verify as an argument. It's more versatile
approach than having expect_bt_bap_stream_ops_released_called_twice
erc. functions, that scales bad.
The function ignores the arhument list order, so that the user does not
have to predict the exact order of function calls.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
This limits the default number of ASEs available to 1.
The value can be overwritten in test case specific parameters
in testcase.yaml file.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
This removes duplicated CONFIG_BT_ISO_MAX_CHAN config setting and leaves
the default value set to 1.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
This avoids unexpected assert that may happen when the client tries to
QoS configure ASE that is in state which does not allow to be configured.
In such case the assert shall not be not be triggered, as it's not stack
fauly. The assert check has been moved after the state check, so the ASCS
implementation will just return an error code to the client.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
This adds missing tests for invalid operations initiated by
locally or by client on ASE in Releasing state.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
This removes 2 tests related to ASCS handling ACL disconnection.
c3c83c7049 modified the ACL disconection
behavior, so that ASE goes directly to idle state, not waiting in
releasing state for CIS disconnection. Thus the tests where state
machine waits for CIS disconnection can be removed now.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
This fixes CCC subscriptions that were removed if the automatic
resubscription was aborted by ACL disconnection.
As the client renews subscriptions, there is no point of removing those
if the link is disconnected unexpectedly.
The API user won't be notified about the failure, as the automatic
resubscriptions are implicit, and after reconnection the subscriptions
will be still valid.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
Zephyr by default renews the characteristic value subscription on every
reconnection. If the ACL is disconnected in the middle of this
procedure, all the subscriptions waiting to be renewed are removed, even
if the device was successfully subscribed already.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
Daniel Leung