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3 Commits

Author SHA1 Message Date
Mateusz Holenko cb677febb1 dts: riscv: Fix a typo in riscv,isa for mpfs 
The RISC-V ISA extension is called `Zifencei` instead of `Zfencei`.

Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
 2023-12-12 16:26:17 +01:00
Conor Paxton 13f8d80930 dts: riscv: add all contexts and devices to the plic on mpfs 
Microchip's PolarFire SoC has a total of 9 contexts associated with the
Platform Interrupt controller (PLIC). the E51 core has a single context
(M Mode), and the application processor U54 cores have two each (M mode
and S mode, respectively)

While we are at it, there are a total of 186 interrupts, not 187.

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
 2023-12-06 17:54:29 +00:00
Conor Paxton 3c7f10f8e1 dts: riscv: rename PolarFire SoC using device family name 
Microchip's PolarFire SoC (device family name: MPFS) is not specific to
the Icicle Kit. Rename the devicetree sources to be more generic and to
align with Linux and allow for other development boards to adopt.

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
 2023-12-06 17:54:29 +00:00