Commit Graph

6 Commits

Author SHA1 Message Date
Andy Ross f35d02cef0 soc/x86: Clean up EHL kconfigs
Cleanup along the same lines as the last change to APL/up_squared.
Make sure all hardware configuration is at the board level where it
belongs and not in the soc, don't play games with defaulting timer
drivers.  Unify the configuration where possible and make it clearer
which setting goes with which driver.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-07 16:48:58 -04:00
Andrew Boie b0b7756756 x86: pre-allocate address space
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.

We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.

The default address space size is now 8MB, but this can be
tuned by the application.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Anas Nashif e980848ba7 Revert "x86: pre-allocate address space"
This reverts commit 64f05d443a.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Andrew Boie 64f05d443a x86: pre-allocate address space
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.

We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.

The default address space size is now 8MB, but this can be
tuned by the application.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Johan Hedberg 0970e42334 boards: x86: ehl_crb: Add board variant for Slim Bootloader
When using Slim Bootloader the UART configuration isn't quite the same
as with the UEFI BIOS. In particular, UART2 is hidden in PCIe and is
instead accessible using a fixed MMIO address. Interrupts are also not
supported for this UART currently.

The simplest way to create builds against this special BIOS/bootloader
setup seems to be to create a new board variant/definition which lets
us provide a custom device tree overlay as well a dedicated Kconfig
default configuration.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-18 15:45:58 -05:00
Johan Hedberg 7c70032d1f boards: x86: Add ehl_crb board definition
Add initial definition for the Elkhart Lake CRB board.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-12 14:16:23 +02:00