Currently there is no way to support running a board on multiple
emulation platforms nor to choose a desired emulation platform for the
simulation to be run on. This commit introduces a new
SUPPORTED_EMU_PLATFORMS list, which defines available emulation
platforms for a given board.
Fixes#12375.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit removes usage of Xen emulated PL011 SBSA UART in favor of
Xen PV console minimal implementation. Now boot log and application
output can be directly taken from hypervisor domain console, instead of
virtual UART.
Also Xen VM doc was updated according to these changes.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Pick those common node in 'fvp-baser-aemv8r.dts' to 'fvp-aemv8r.dtsi'
which reside in 'dts/arm64/fvp-aemv8r' directory.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This is the initial Zephyr support for Intel SoC FPGA Agilex support.
Agilex has quad-core 64-bit Arm Cortex*-A53.
This patch build Zephyr for Agilex development kit with 256KB SDRAM and
support hello_world sample code. The Zephyr will need to be loaded by
Intel Arm Trusted Firmware (ATF).
Agilex Zephyr boot flow:
FSBL:ATF BL2(EL3) -> SSBL:ATF BL31(EL3) -> OS:Zephyr(EL2->EL1)
Intel ATF can be loaded from:
https://github.com/altera-opensource/arm-trusted-firmware.git
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
The ITS needs a number of table, so HEAP must be reserved for runtime
allocation (1MiB is a round and convenient value):
- Redistributor:
* 64K table for all redistributors
* 64k for each redistributors
- ITS:
* 4K collection table aligned on 4K
* 4K x 128 device table aligned on 4K
This makes 11x64K to permit all allocations to success.
Note, will need 64K HEAP_MEM per CPUs added.
This doesn't necessarily include the Interrupt Translation Table,
which are 256bytes aligned tables, for reference a 32 ITEs table
needs 256bytes.
With 14x64K HEAP, up to 116 ITT tables of 32 ITEs can be allocated.
A specific HEAP_MEM_POOL_SIZE as been added to arm64_gicv3_its test
for the fvp_base_revc_2xaemv8a board to satisfy all memory allocation
constraints for 256 ITT tables with 32 ITEs allocations.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
By default fvp_base_revc_2xaemv8a used 17bits per DeviceID, limit it to
16bits for the PCIe MSI/MSI-C use-case and save some memory.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
It may be needed to run Zephyr at EL1NS level with `CONFIG_ARMV8_A_NS`
In order to run at EL1NS, you'll need a proper Firmware loaded in the
FVP model to run Zephyr at non-secure EL3.
The ARM TF-A for FVP can used to run Zephyr as preloaded BL33.
This adds the necessary cmake scripts to load the TF-A binaries and
load Zephyr as preloaded BL33 payload.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add psci and more cpu nodes into fvp_baser_aemv8r.dts. The purpose
of it is perparing to support SMP.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Add support for the FVP Base RevC 2xAEMv8A board to be emulated using
the same FVP. For now the virtual platform is only exposing one core and
the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...).
INFO - Total complete: 256/ 256 100% skipped: 933, failed: 0
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
1. add a seperate 2 cores SMP board configuration to run in Jailhouse
inmate Cell, root Cell Linux will use Core0 and Core1, Zephyr will
run on Core2 and Core3.
2. Refine the code of dts, move SoC common dts nodes into dtsi fiel in
dts/arm64/nxp/ directory.
3. Add myself to be code owner of directory dts/arm64/nxp/.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
It doesn't hurt always having the image header and generating the binary
output. I find myself constantly setting those to 'y', so make it
definitive.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Currently the SRAM location is fixed for all the boards derived from
qemu_cortex_a53. While this is acceptable when the image is directly
loaded in SRAM by QEMU, in some cases Zephyr can be loaded in RAM by
another piece of software or by semihosting at a different address
before jumping into it.
When for example TF-A is used and Zephyr is run as BL33 payload using
QEMU, in this case the default location in RAM is at a different
address (when preloaded BL33 base address is not used).
To address these cases, move the SRAM location into the board-specific
DTS so that it can be adjusted on a board by board basis.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add essential files to create a new board. Enable arch timer, uart,
multi-threading. Set memory map for flash and sram. The new board name
is fvp_baser_aemv8r with the fvp_aemv8r_aarch64 soc.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Filip Kokosinski