reg value should match value provided within node name (as in pll@2).
Fix this to avoid warning.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks node and clocks to stm32l5 series.
PLL binding is reused from stm32l4 series.
Matching binding is updated to document that.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks nodes for F0/F3/G0/G4 series.
For F0 and G0 series, update compatible for rcc node
to specify use of dedicated "st,stm32f0-rcc" compatible.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove default pll settings to ensure pll users are correctly
configuring all prescalers on purpose and avoid surprises.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds flash clock settings in device tree for stm32h7
series such that the stm32h7 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Provided nodes reflect the clock tree of each series.
Clock nodes are disabled by default but populated with default
start up configuration. Main reason is the we don't want to
impact boards using Kconfig based clock configuration for now.
Exception to these rules:
- syslck: Default enabled, clock frequency and clock source not
provided
- pll: clock source not provided
This is made on purpose so that errors are triggered if parameters
essential to the board configuration are not provided.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
i2s1 is not present in all stm32f4 series. So moving the i2s1 node
from the top level stm32f4 dtsi file to the stm32fxx specific dtsi
files. Also in stm32f429zi, the sequence starts from i2s2, this commit
helps in having the right channel number.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
STM32G0 is supported by the st,stm32-dma-v2 driver.
This commit adds dma1 and dmamux dts bindings
for stm32g03x, stm32g05x and stm32g07x.
For stm32g0bx additionally dma2 is added.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This patch adds flash clock settings in device tree for stm32wb
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32l4
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32l1
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32g4
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32g0
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Enabling pwm on timer3 for stm32l1 series in dtsi.
Adding other timer nodes for pwm capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Enabling PWM on timer1 for STM32F2 platform in dtsi.
Adding other timers nodes for PWM capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Move the definition of the two IPC RAM blocks from `#define`'s in family
linker scripts to proper devicetree nodes. Use the devicetree nodes to
generate the memory regions.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Cortex M0 Series only have two interrupt priority bits,
nevertheless all series set the priority per default to the invalid
value of 7.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The adc1 of the stm32f373 uses an address space and a bus that are
different from the other microncontrollers of the f3 family. So, let's
remove the adc1 node from the stm32f3.dtsi and add it directly, with
respective correct values, in each of the SoC variant files.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
STM32L011 and STM32L031 do not support USART1.
This commit moves the definition of the node to only
be present for MCUs which support the peripheral.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
TIM7 peripheral was defined for all STM32L4 chips
in the device tree when not every chip supports it.
This commit moves the node so that only chips
which support the peripheral have the node defined.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
The device tree includes CAN node can1 for all
STM32L4 chips when in fact they don't all support it.
This affects STM32L412xx and STM32L422xx.
Fixes#33896
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
This commit creates two new files in the device tree
1. stm32l412X8.dtsi
2. stm32l412XB.dtsi
This will specifcally add stm32l412X8 to the device tree
which was not supported before. Also the memory
for stm32l412XB was not defined specifically before.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
This patch introduces the support of the Low Power Timer
for the STM32L5xx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enabling I2C-1,2,3 support for STM32F2 platforms in dtsi.
This has been tested with mpu6050 sample application on I2C-1.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Francois Ramu