Do not allocate TxFIFO in a way that could corrupt Endpoint Information
Controller data (stored at DFIFO Depth address) or access locations
outside the SPRAM.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
For code clarity, this commit adjusts the use of `return` statements
in functions with a void return type as follows:
- Transform `return foo();` into separate statements:
`foo();`
`return;`
- Remove unnecessary `return` statements when
they don't affect control flow.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Do not schedule isochronous data on current frame. While doing so can
work at Full-Speed, it is pretty much impossible to do it quickly enough
at High-Speed.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Move the transfer process codes to work context becuase
it lock the mutex, move bus reset process codes too
because it calls some common udc apis (they may add
mutex lock in future).
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Change ensures that `dwc2_handle_xfer_next` would notify upper layer if
`dwc2_tx_fifo_write` fails. This is necessary to ensure that upper layer
is aware of the failed TX for the submitted transfer. It also ensures
that the submitted transfer is removed from the TX queue.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Move the network buffer header file from zephyr/net/buf.h to
zephyr/net_buf.h as the implementation now lives outside of the networking
subsystem.
Add (deprecated) zephyr/net/buf.h header to maintain compatibility with old
file path.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
A connected state was reported as a disconnected state.
This led to wrong reports of the connected state to all systems
relying on it.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
This driver is mostly rewritten from scratch, with some parts borrowed
from the usb_dc_rpi_pico driver implemented by Pete Johanson.
This driver does not use any function from RPI PICO HAL and actually
could be furter improved to not use any defines or types from the HAL as
they are confusing and overdo it with volatile qualifiers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Select PINCTRL subsystem by drivers which require it.
Prevent the need from enabling this symbol at board or soc level.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
In the IT82xx2 chip, the ready bit is automatically cleared by
hardware. When setting other bits, there is a chance that the ready bit
hasn't been cleared yet, leading to unexpected USB transactions. This
change ensures that the ready bit is always set to '0' when setting the
endpoint control value.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Save power when the bus is suspended by entering hibernation if
hibernation support is enabled and controller supports hibernation.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add Power and clock gating control register to register map and
appropriate bit macros. Add missing GHWCFG4, GLPMCFG and GPWRDN bits.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Remove the early max packet size check on endpoint activation, because
there are valid use cases where the max packet size is not multiple of 4
and the stack won't perform multi-transaction transfers. Example use
case is UAC2 explicit feedback endpoint that has Max Packet Size equal
3 when device is operating at Full-Speed.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Fail TxFIFO write if the endpoint is not activated, because there is
essentially no fifo assigned. Writing to not activated endpoint is
possible, but it does tend to corrupt fifo number 0 which is used for
control transfers. USB stack should not really be attempting to write to
endpoints that have not been activated (ep_enable called).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Store SOF frame number and use the information to set the Even/Odd
microframe bit when enabling isochronous endpoints. Reject received
isochronous data if number of packets received does not align with
received PID.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
RxFLvl interrupt should only handle the actual data movement from RxFIFO
to the buffer. OUT transfers are completed in XferCompl handler both in
DMA and Completer mode. This reduces code size by avoiding having
separate code paths based on operating mode.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Function dwc2_set_dedicated_fifo() calls dwc2_flush_tx_fifo() before the
diepctl register is written. The register will be only written after the
dwc2_set_dedicated_fifo() finishes. Solve the problem by passing fifo
number directly instead of endpoint address to dwc2_flush_tx_fifo().
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add all register bit defines necessary for isochronous transfers. Clean
up the endpoint transfer size register defines clearly separating IN and
OUT registers because they do use different bit fields. Add alternate
bit names for bits that do have different meaning based on configured
endpoint transfer type.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The CONFIG_USB_MCUX_CONTROLLER_TYPE choice config
is not necessary, let's just remove it. Theoretically,
if there was an SOC with the EHCI and LPCIP3511, then
it might cause a build error, but there is no SOC
which is supported on this legacy driver that has that.
Remove all settings of it in the SOC files.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
set high_bandwidth and use the cfg->mps to set
ep_init.maxPacketSize because NXP MCUX controller
driver supports additional transaction bits in
maxPacketSize.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Instead, use the helper to get the size field from the MPS value.
MPS value may contain information about additional transaction
per microframe (bits 12..11).
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Make driver aware of High-Bandwidth endpoints both in Completer and
Buffer DMA mode. In Completer mode TxFIFO must be able to hold all
packets for microframe, while in Buffer DMA mode space enough for two
packets is sufficient.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
DMA is capable of packetizing transfers on its own and the driver
doesn't need to check available TxFIFO size when scheduling DMA
transfer.
Split packets on DWORD boundary when writing more than one packet to
TxFIFO in completer mode.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add macros for converting between Max Packet Size and total payload
length. Allow drivers specify whether endpoint supports high-bandwidth
interrupt and high-bandwidth isochronous transfers.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Convert users of net_buf_put() and net_buf_get() functions to use
non-wrapped putters and getters k_fifo_put() and k_fifo_get().
Special handling of net_bufs in k_fifos is no longer needed after commit
3d306c181f, since these actions are now
atomic regardless of any net_buf fragments.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The processing order is relevant if the IRQ handler call is delayed and
multiple interrupts are pending. Handle USB SoF before other interrupts
to ensure that it would be reported before other USB events (e.g. before
completed USB data transfers).
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Add an opaque pointer to store upper layer private data and initialize
it with the USB device context during controller initialization. Use the
pointer in event processing to get the correct context.
Fixes commit 48f2a4bc1a
("usb: device_next: remove initialized state checks in event processing")
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Force disabling the USB OTG HS and PHY clock during sleepmode
By default, that clock is enabled by clock gating during sleep
mode. Like stm32H7, it has to be kept running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Special sequence to enable clock and power for the OTG HS
peripheral of the stm32U59x serie
This code is based on the stm32Cube HAL_HCD_MspInit/DeInit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Force disabling the USB OTG HS and PHY clock during sleepmode
By default, that clock is enabled by clock gating during sleep
mode. Like stm32H7, it has to be kept running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Special sequence to enable clock and power for the OTG HS
peripheral of the stm32U59x serie
This code is based on the stm32Cube HAL_HCD_MspInit/DeInit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Set the correct the phy_itface depending on the setting
Save few lines after resetting the priv->pcd structure
with the memset
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Driver includes wrong header zephyr/usb/usb_device.h and uses defines
from include/zephyr/drivers/usb/usb_dc.h.
Also fix udc_ep_enable() implementation in general. HAL_PCD_EP_Open()
takes the ep_type parameter as uint8_t integer type and the shim driver
should not just pass int type.
It is recommended that drivers use ep_cfg or cfg for struct
udc_ep_config, fix this as well.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The global otg interrupt hs/fs is enabled by the udc_stm32
driver. Get it in the list of interrupts of the OTG node.
Use UDC_STM32_IRQ naming.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove BUILD_ASSERT for Internal DMA and DCACHE if both are enabled, and
enable Internal DMA support by default.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
UDC_BUF_POOL_*_DEFINE macro will place buffer pool in __nocache
section if NOCACHE_MEMORY is enabled.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Introduce UDC_BUF_POOL_*_DEFINE macros based on NET_BUF_POOL_*_DEFINE
macros but use our own version of alloc and unref callbacks to get
buffers with specific alignment and granularity. Also, do not use ref
callback because it breaks alignment.
Also introduces helper macros for defining and checking UDC
driver-compliant static buffers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
When dynamic fifo sizing is enabled the driver can assign fifo size
lower or equal to the reset value. Software must respect the maximum
sizes because fifo width registers are optimized during synthesis and
the larger values simply get discarded.
Use 16-bit values for FIFO depths because maximum FIFO depth the vendor
can configure the DWC2 otg is 32768.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The DPSRAM ports can run at different clocks, this is the default
configuration, follow the advice in the datasheet and wait 3 nop
instructions before setting the AVAILABLE bit.
It can be observed that when the controller is continuously sending data
to the host, it rarely has a 0-byte transaction instead of a short
packet. The reason for this is not easy to find, it also seems to depend
on the runtime of individual components. This may fix the problem, but
there is no sure proof that this is the solution.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Seems like not all stm32 devices define USBD_HS_SPEED in the HAL, only
check for USBD_HS_SPEED if defined. Fixes a build failure with the new
stack on F1 MCUs.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
A function, such as CDC ECM, can set the ZLP flag to handle a
class-specific protocol. This is not to be confused with the ZLP role in
control transfers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Tomasz Moń