This interrupt controller is a designware IP that combines several
sources of interrupt into one line that is then routed to the parent
controller.
This implementation supports only the regular irqs with no support
for priority filtering and vectored interrupts. Firqs are also not
supported.
Change-Id: I8bdf6f8df4632b6d7e8a3ba9a77116771d034a48
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rajavardhan Gundi