We re-wrote the xtensa arch code, but never got around
to purging the old implementation.
Removed those boards which hadn't been moved to the new
arch code. These were all xt-sim simulator targets and not
real hardware.
Fixes: #18138
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Remove the handcoded multi-level IRQ values in device tree. We now are
able to generate the encoded multi-level IRQ value.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This provides an implemention for z_soc_irq_is_enabled()
as it is needed for multi-level interrupts.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The spi_dw driver used system clock frequency
as a base for SPI bus frequency calculation.
This commit corrects that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Found a few annoying typos and figured I better run script and
fix anything it can find, here are the results...
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add dts fixup definitions for low power sram base address and size
- DT_LP_SRAM_BASE
- DT_LP_SRAM_SIZE
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
The i2s_cavs.c driver manipulates cache lines before commencing
any DMA transfers. With write-back cache, if the DMA receive
buffer is not aligned to the cache lines, the data around
the buffer will be invalidated and may never written to memory.
Since the driver takes an external memory slab as buffer and
there is no easy way to force cache line alignment on
the application side, set the cached region to write-through
to avoid potential issue.
Fixes#13223
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This macro is slated for complete removal, as it's not possible
on arches with an MPU stack guard to know the true buffer bounds
without also knowing the runtime state of its associated thread.
As removing this completely would be invasive to where we are
in the 1.14 release, demote to a private kernel Z_ API instead.
The current way that the macro is being used internally will
not cause any undue harm, we just don't want any external code
depending on it.
The final work to remove this (and overhaul stack specification in
general) will take place in 1.15 in the context of #14269Fixes: #14766
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Maybe this is some "just in case" thing that got copied around. There's
no need to have a blank line at the beginning or end of Kconfig files.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
The IRQ defined in DTS has already been shifted so there is
no need to shift again in dts_fixup.h.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Due to fake IDT_BASE address, zephyr_prebuilt.elf is about 1.1GB
in size due to all the empty space between end of SRAM and IDT_BASE.
So move the IDT_BASE to the empty space just after SRAM. The section
will be discarded in the final zephyr.elf so it should not be a big
issue. After this change, zephyr_prebuilt.elf is now a bit smaller
than 5MB.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Previous rename from CONFIG_* to DT_* left a few remaining
CONFIG_*. So rename them manually now.
Fix#13753
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add SOC level macros to flush and invalidate data cache.
Individual drivers can use this macro instead of defining
their own macros.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
This reverts commit c9ace83c89 which
bypasses setting cache attributes.
The previous cache attributes actually set the text/data/etc.
sections to be inaccessible. So fix it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Commit ce7ed18989 moved CONFIG_SRAM_*
so dts_fixup.h needs to be updated for properly generated linker
script.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move IRQ number encoding out of dts_fixup.h and into the dtsi files.
For now just change devices on the dw_intc.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The starting 192kB SRAM is reserved for the mcubootloader. Exclude
this region while building an application to be loaded by mcubootloader.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
FIFO_DEPTH should be in the SoC's Kconfig as this is a
configuration of SPI master controller in SoC.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.
Fixes#11268.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
CONFIG_TEXT_SECTION_OFFSET allows the entire image to be moved
in memory to allow space for some type of header. The mcubootloader
can boot only such images which reserve some space for the header.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Since pinmux configuration is board dependent and is now under
boards/xtensa/intel_s1000, the configuration in soc.c is removed.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
When users are configuring applications they are given the option
to enable the DesignWare SPI driver. But they should not be given this
option on SoCs that don't have the DesignWare SPI HW.
This commit hides the driver by default by introducing the config
option HAS_SPI_DW.
Fixes: #10825
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
All drivers require DTS for their primary SPI settings.
Removing SPI_[0-9]_NAME config option added some more samples changes.
Usage of these options there was anyway not relevant.
Fixes#11064
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The majority of cases of CONFIG_I2C_x_IRQ_PRI should be
DT_I2C_x_IRQ_PRI. So go ahead and fix them up. Only the i2c_nios
driver still uses Kconfig for getting priority.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The firmware starts us with an already-initialized UART and a simple
ROM hook. Use that as the default printk handler so we can log in
very early boot. It will be overriden later (as it happens, by
another handler based on the same firmware hooks).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Andrew Boie