Enable Mailbox support on 96Boards Avenger96 board. This will help
communicating to CortexA7 core.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Add onboard LEDs on 96Boards Avenger96 board. There are 4 user LEDs
on this board but only 3 are enabled. This is due to the fact that
LED0 is connected to unavailable PortZ. Hence, LED0 is ignored and
remaining LEDs are enabled starting from index 0.
Once PortZ is added, this will be fixed.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).
On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.
On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.
Fixes#17188
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add board support for 96Boards Avenger96 board from Arrow Electronics
based on STM32MP157A MPU from ST Microelectronics. This board is one
of the consumer editions boards of the 96Boards family following the
Extented CE form factor. More information about this board can be found
in 96Boards website: https://www.96boards.org/product/avenger96/
By default Zephyr console output is available via RAM console, but it
can also be changed to UART7 exposed as UART0 on 40 pin LS header.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
David B. Kinder