Commit Graph

30 Commits

Author SHA1 Message Date
Daniel Leung b7eb04b300 x86: consolidate x86_64 architecture, SoC and boards
There are two set of code supporting x86_64: x86_64 using x32 ABI,
and x86 long mode, and this consolidates both into one x86_64
architecture and SoC supporting truly 64-bit mode.

() Removes the x86_64:x32 architecture and SoC, and replaces
   them with the existing x86 long mode arch and SoC.
() Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64.
() Updates samples and tests to remove reference to
   qemu_x86_long.
() Renames CONFIG_X86_LONGMODE to CONFIG_X86_64.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-10-25 17:57:55 -04:00
Peter Bigot 6e5db350b2 coccinelle: standardize k_sleep calls with integer timeouts
Re-run with updated script to convert integer literal delay arguments to
k_sleep to use the standard timeout macros.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-10-09 08:38:10 -04:00
Andy Ross d1200d2155 tests: Never disable SMP
Disabling SMP mode for certain tests was a one-release thing, done to
avoid having to triage every test independently (MANY are not
SMP-safe), and with the knowledge that it was probably hiding bugs in
the kernel.

Turn it on pervasively.  Tests are treated with a combination of
flagging specific cases as "1cpu" where we have short-running tests
that can be independently run in an otherwise SMP environment, and via
setting CONFIG_MP_NUM_CPUS=1 where that's not possible (which still
runs the full SMP kernel config, but with only one CPU available).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-09-26 16:54:06 -04:00
Charles E. Youse 0f98cdd457 arch/x86: tests/cmsis: disable some CMSIS tests in 64-bit mode
The CMSIS layer doesn't like large stacks, and x86 in long mode
requires large stacks, so we disable these tests for now (as was
previously done on the x86_64 port for the same reasons).

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-15 11:33:47 +08:00
David B. Kinder 60136f00cb doc: add how to exit from QEMU in samples
While trying out the hello_world sample built for QEMU, I was expecting
the sample app to exit and I'd return to a command prompt.  Nope.  You
need to exit QEMU manually, so add that step to the sample instructions.
Looking around, there are more uses of QEMU like this that could use
this added step after running the sample app.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-09-02 12:06:08 -04:00
Ioannis Glaropoulos 8dc83c1d94 tests: several tweaks for passing tests on qemu
This commit includes tweaks in several tests, so
that the tests can be passing on ARM QEMU targets,
mps2_an385 and mps2_an521 with Qemu 4.x release.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-08-08 21:56:45 +02:00
Andy Ross ee4c23cc1f CMSIS v2: Work around time unit confusion
The current CMSIS v2 implementation is clearly assuming that timeout
arguments being passed to e.g. osDelay() are in units of Zephyr ticks,
not milliseconds as specified by ARM or (inconsistently) assumed by
our test code.

Most tests work with the ~100 Hz default tick rate, but they tend to
fail on precision issues at higher tick rates.  Force the CMSIS v2
applications to be 1000 Hz for now as a workaround, and detect the
mismatch as a build failure.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-07-02 22:52:29 -04:00
Andy Ross f288d1e4a7 tests: samples: Apps shouldn't set tick rate
Tick rate is becoming a platform tunable in the tickless world.  Some
apps were setting it due to requirements of drivers or subsystems (or
sometimes for reasons that don't make much sense), but the dependency
goes the other way around now: board/soc/arch level code is
responsible for setting tick rates that work with their devices.

A few tests still use hard-configured tick rates, as they have
baked-in assumptions (like e.g. "a tick will be longer than a
millisecond") that need to be addressed first.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-07-02 22:52:29 -04:00
Anas Nashif 9ab2a56751 cleanup: include/: move misc/printk.h to sys/printk.h
move misc/printk.h to sys/printk.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif 5eb90ec169 cleanup: include/: move misc/__assert.h to sys/__assert.h
move misc/__assert.h to sys/__assert.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif f2cb20c772 docs: fix misspelling across the tree
Found a few annoying typos and figured I better run script and
fix anything it can find, here are the results...

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-19 15:34:13 -05:00
Nicolas Pitre 6311766d9a pointer-type args: cast appropriately to be 64-bit compatible
Using void pointers as universal arguments is widely used. However, when
compiling a 64-bit target, the compiler doesn't like when an int is
converted to a pointer and vice versa despite the presence of a cast.
This is due to a width mismatch between ints (32 bits) and pointers
(64 bits). The trick is to cast to a widening integer type such as
intptr_t and then cast to
void*.

When appropriate, the INT_TO_POINTER macro is used instead of this
double cast to make things clearer. The converse with POINTER_TO_INT
is also done which also serves as good code annotations.

While at it, remove unneeded casts to specific pointer types from void*
in the vicinity, and move to typed variable upon function entry to make
the code cleaner.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-06-12 08:20:52 -07:00
Andrew Boie 4d4cc4ddc3 samples: philosophers: pause before main() exit
On some systems the sample was failing validation because
the coverage data would be emitted before the sample had
a chance to print anything else.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-06-06 09:29:12 -07:00
Andrew Boie 930a5f8fb7 samples: cmsis philosophers: adjust stack size
Fixes crashes when running with code coverage
enabled.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-06-06 09:29:12 -07:00
Anas Nashif 3ae52624ff license: cleanup: add SPDX Apache-2.0 license identifier
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier.  Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.

By default all files without license information are under the default
license of Zephyr, which is Apache version 2.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-07 08:45:22 -04:00
Anas Nashif da5f185e06 samples: add test identifier
Add unique identifier instead of just 'test' for samples.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-03-29 17:44:11 -04:00
Patrik Flykt 24d71431e9 all: Add 'U' suffix when using unsigned variables
Add a 'U' suffix to values when computing and comparing against
unsigned variables.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-28 17:15:58 -05:00
Andy Ross a334ac2045 tests: Mass SMP disablement on non-SMP-safe tests
(Chunk 1 of 3 - this patch was split across pull requests to address
CI build time limitations)

Zephyr has always been a uniprocessor system, and its kernel tests are
rife with assumptions and outright dependence on single-CPU operation
(for example: "low priority threads will never run until this high
priority thread blocks" -- not true if there's another processor to
run it!)

About 1/3 of our tests fail right now on x86_64 when dual processor
operation is made default.  Most of those can probably be recovered on
a case-by-case basis with simple changes (and a few of them might
represent real bugs in SMP!), but for now let's make sure the full
test suite passes by turning the second CPU off.  There's still plenty
of SMP coverage in the remaining cases.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-02-28 13:02:20 -06:00
Andrew Boie feab37096b libc: fix CONFIG_STDOUT_CONSOLE semantics
The intent of this Kconfig is to allow libc stdout
functions like printf() to send their output to the
active console driver instead of discarding it.

This somehow evolved into preferring to use
printf() instead of printk() for all test case output
if enabled. Libc printf() implementation for both
minimal libc and newlib use considerably more stack
space than printk(), with nothing gained by using
them.

Remove all instances where we are conditionally
sending test case output based on this config, enable
it by default, and adjust a few tests that disabled
this because they were blowing stack.

printk() and vprintk() now work as expected for
unit_testing targets, they are just wrappers for
host printf().

Fixes: #13701

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-26 08:00:33 -06:00
Andy Ross 9ff319dc52 samples/portability/cmsis_rtos_v2/philosophers: Exclude qemu_x86_64
This is hitting a stack overflow (probably the same reason xtensa is
also excluded -- both are stack-hungry platforms), but with CMSIS
there is a fixed cap of 512 bytes that can't be extended.  So
whitelist this sample.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-02-08 14:49:39 -05:00
Spoorthi K 8c1eecbada samples: cmsis_rtos_v2: Resolve control flow issue
Resolve control flow issue in cmsis_rtos_v2 sample.

Fixes: #12295

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2019-02-06 21:34:20 -05:00
Spoorthi K cd1af7333e samples: cmsis_rtos_v1: Resolve control flow issue
Resolve control flow issue in cmsis_rtos_v1 sample.

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2019-02-06 21:34:20 -05:00
Andy Ross c2c9265b7d tests: cmsis: Disable two cmsis portability tests on x86_64
These two tests are hitting a stack overflow on x86_64 (not entirely
surprisingly), but can't just increase stack size because there is an
assert in the CMSIS compatibility layer that stacks be under 512
bytes.  Just disable for now.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-01-11 15:18:52 -05:00
Anas Nashif 5060ca6a30 cmake: increase minimal required version to 3.13.1
Move to latest cmake version with many bug fixes and enhancements.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2019-01-03 11:51:29 -05:00
Spoorthi K b1e912bdb3 samples: cmsis_rtos_v2: Demo on msgq and timers synchronization
The sample application demonstrates usage of threads, message queue
and timer APIs in CMSIS RTOS V2.

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2018-12-21 10:28:10 +01:00
Spoorthi K cea0982f23 samples: cmsis_rtos_v2: Demo with Dining Philosopher's algorithm
The sample application to demonstrate dining philosopher's problem
implementation using CMSIS RTOS V2 APIs with semaphores and mutexes
as resources (forks).

The application makes use of CMSIS_RTOS_V2 APIs on threads, semaphores
and mutexes.

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2018-12-21 10:28:10 +01:00
Kumar Gala c9e5a27f41 samples: cmsis_rtos_v1: Disable tests on qemu_xtensa
We get an intermittent fail when running on qemu_xtensa.  Disable this
sample for now on that platform to allow sanitycheck / CI to pass for
other PRs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-12-07 08:37:07 -05:00
Anas Nashif 60f7052bc4 samples: cmsis_rtos_v1: remove tracing test
This is not relevant to the test.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-12-07 08:17:37 -05:00
Spoorthi K 34c4d0e3dd samples: cmsis_rtos_v1: Demo on msgq and timers
Sample to demonstrate usage of message queue, threads
and timers with CMSIS RTOS V1 APIs.

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2018-12-06 12:19:23 -05:00
Spoorthi K 940ee4e7e5 samples: cmsis_rtos_v1: Demo with Dining philosopher's problem
Sample application to demonstrate usage of cmsis_rtos_v1 APIs
with dining philosopher's problem implementation.

This covers semaphores, mutex and thread APIs of CMSIS RTOS V1.

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2018-12-06 12:19:23 -05:00