Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add Atmel SAM I2C Two-wire Master Interface (TWIM). The SAM
i2c controller have specifics regs depending of operation mode
Master/Slave and the bindings are for Master only.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The sam4l pinctrl contains two entries with wrong values. Fix the
typo to create valid pinctrl map.
Fixes#28538.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The peripheral is the same on the SAMD20 and SAMD21 except for
different clock and interrupt settings. There is no DAC on the SAMR21.
Leave disabled by default as the DAC is fairly power hungry.
Signed-off-by: Michael Hope <mlhx@google.com>
Now that the patches have landed, enable more of the peripherals on
the board.
In particular:
* Enable PWM on the LED
* Enable the SPI, USB, and DMA
* Enable the bootloader support
* Add to the PWM and SPI tests
* Call these out in supported.yaml
Signed-off-by: Michael Hope <mlhx@google.com>
This commit adds the device tree TCC (Timer/Counter for Control
Applications) peripheral definitions for the Atmel SAM D5x and E5x
series SoCs.
The SAM D5x/E5x series SoCs have five instances of the TCC peripheral:
TCC# Channels Waveform Output Counter Size
0 6 8 24-bit
1 4 8 24-bit
2 3 3 16-bit
3 2 2 16-bit
4 2 2 16-bit
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAMD21 series has three timer/counters with a mix of channels and
resolutions. Note that the SAMD20 only has TC peripherals and no TCC
peripherals which is why the changes are in samd21.dtsi.
Signed-off-by: Michael Hope <mlhx@google.com>
This allows referencing the CPU in the board-specific DTS file.
Also fix warnings by making the addresses lower case.
Signed-off-by: Michael Hope <mlhx@google.com>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert sam_xdmac driver to utilize devicetree. As part of the
controller binding we specify that dmas should contain a channel and the
perid for the DMA transaction.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Atmel SAM D5x and E5x series SoCs include the ARM memory protection
unit that supports up to 8 memory regions.
This commit adds the missing device tree MPU node to `samd5x.dtsi`,
which is used by both the SAM D5x and E5x series SoCs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree.
We add a property ('calib-offset') for the SAM{D,E}5x family of SoCs
that is the bit position offset from ADC0 BIASCOMP in the NVM Software
Calibration Area Mapping. For ADC0 this is typically 0 and for ADC1
this will be 14.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace DT_FLASH_DEV_NAME with DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL.
We now set zephyr,flash-controller in the chosen node of the device
tree to the flash controller device.
NOTE: For a SoCs with on die flash, this points to the controller and
not the 'soc-nv-flash' node. Typically the controller is the
parent of the 'soc-nv-flash' node).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add clock references for ADC and TC devices. Update the bindings for
these devices to require clocks property and update the dtsi files to
have the clock info.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add pinctl support for the SAM SPI device. We update the SPI
binding to have pinctrl-0 bindings that are expected to have
at least phandles for MISO, MOSI, and SPCK, but might also have
various chip selects as well.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SAM D5x and E5x series SoCs include the "Cortex-M4F" core, not the
FPU-less "Cortex-M4" core.
This commit fixes the incorrect CPU compatible for the SAM D5x and E5x
SoCs (note that this file is included by `same5x.dtsi`, which is used
as the base device tree header for the SAM E5x series).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Reworked adc_sam_afec driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the atmel,sam0-dmac binding under the dma binding dir and add
cell information for channel and trigger source. Update the associated
dtsi files to match these changes.
This is in prep of ATMEL SAM0 SERCOMM devices like UART, I2C, and SPI to
user proper 'dmas' property to specify the dma info to use.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for the GCLK, MCLK, and PM clock controllers. Add bindings
and devicetree nodes associated with these clock controllers. Also add
clock references for the SERCOM peripheral set to allow those drivers
(i2c, spi, uart) to utilize this information.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit renames `samd.dtsi` to `samd2x.dtsi` since this DTS header
is specific to the SAM D2x series and its derivatives (e.g. SAM R21).
Note that the SAM D5x series uses a different DTS header file (i.e.
`samd5x.dtsi`) due to the vast differences, and the future SAM D1x will
have to use a separate DTS header to be sensible anyway.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add pinctl support for the SAM TWI and TWIHS I2C devices. We update
the TWI and TWIHS I2C bindings to have pinctrl-0 bindings that are
expected to have 2 phandles to the TWCK & TWD pinctrl nodes.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add pinctl support for the SAM UART and SAM USART devices. We update
the UART and USART bindings to have pinctrl-0 bindings that are expected
to have 2 phandles to the RX & TX pinctrl nodes.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We add sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The atmel,pins property will be utilized to describe pin mux
configuration. The property will be a phandle-array in which the
phandle points to the given GPIO port the pin is on, the pin number, and
the mux configuration.
This change updates the atmel,sam-gpio binding to support that
phandle-array and updates the associated SoC dtsi files as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds a GMAC instance to the SAM E5x device tree, along with
the refactoring necessary to specify the SAM E5x-specific components.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM4E GMAC version can use only MII as phy-connection-type. This
update the current default RMII value to MII.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit adds a GMAC instance to the SAM 4E device tree.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Replace CONFIG_ENTROPY_NAME with DT_CHOSEN_ZEPHYR_ENTROPY_LABEL. We now
set zephyr,entropy in the chosen node of the device tree to the entropy
device.
This allows us to remove CONFIG_ENTROPY_NAME from dts_fixup.h. Also
remove any other stale ENTROPY related defines in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Group all the GPIO controllers under a pinctl node so that we have a
container for pinmux configuration data.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds a GMAC instance to the SAM V71 device tree, with the
chip revision-specific hardware queue count.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds a GMAC instance to the SAM E70 device tree, with the
chip revision-specific hardware queue count.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds Device-Tree instances of the Flash controller
to the SAM3X, SAM4E and SAM4S series. The Flash-Controller
is used to get the unique device identifier.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
The blocks were moved into the soc block in samd5x.dtsi,
so we also have to move them for the the actual SoC definitions
that inherit from that.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
The amount of lock regions differs between different sam0 MCUs.
saml10: 2
saml11: 4
samd2x: 16
saml2x: 16
samd5x: 32
ASF does not provide a definition for this, so create a new one
in dts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Piotr Mienkowski