hal_espressif repository was updated from esp-idf v4.2
to esp-idf v4.3 to allow latest Espressif chips integration.
As a consequence, it added a few changes in drivers
and peripherals. To maintain bisectability, changes in this
PR cannot be split. Here are some details:
wifi: update linker script by adding libphy and new attributes.
spi: update some APIs and fixed missing wait_idle check
west.yml: esp32: update hal to new version
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This fixes missing PPP iterable and adds all
common-rom.ld iterables.
ESP32 and esptool does not support more then 16 segments, which
blocks including common iterables section as is.
This partially reverts commit ad0bf94f77
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Align cavs25 with cavs15/18 and add memory segment for uncached mapping
of the SRAM to linker script. Assign sections to uncached and cached
segments as done in cavs15/18.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
When we link in crtbegin.o for C++ exception support we end up pulling
in the .tm_clone_table section. We need to update the linker scripts
to handle this. soc/xtensa/sample_controller/linker.ld was already
updated, this fixes the others.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixes part of: #32448
This commit updates the CMake CMAKE_CXX_LINK_EXECUTABLE to include
crtbegin.o and crtend.o at the right locations when linking with gcc.
It also updates linker scripts to ensure proper location of the
exception header frame sections.
This ensure proper handling of exceptions for those architectures
- x86
- xtensa
- riscv32
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Z_ITERABLE_SECTION_ROM symbols were empty, meaning
that those symbols were not taking place in the linker script.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the missing .cached section on cAVS 2.0 and 2.5 to fix
compiler warnings.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
PLATFORM_RESET_MHE_AT_BOOT and
PLATFORM_DISABLE_L2CACHE_AT_BOOT have to be defined on cAVS 1.8
too, without them secondary cores cannot be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
uncache_to_cache(), cache_to_uncache() and is_uncached() macros
are currently unused in Zephyr, besides the former two are
dangerous because they add and subtract an offset instead of
masking and unmasking a bit, which can lead to wrong addresses
if applied repeatedly. Remove these macros for now, we can
re-add them later if needed in their fixed versions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently only cAVS 1.5 Kconfig selects ARCH_HAS_COHERENCE,
which is wrong. cAVS 1.8, 2.0 and 2.5 have to select it too.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
SMP support on cAVS is implemented by using uncached addresses
for all writable data sections except for stack, i.e. for .data,
.bss and some other specialised ones. So far that has been
implemented for cAVS 1.5. This patch does the same for cAVS 1.8.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Allow SMP processing for SOF on ADSP. Note, that after this
SOF will build with SMP support enabled on all cAVS versions,
but secondary cores will remain disabled unless an SMP
topology is loaded by the host.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
With SOF secondary cores are booted later at run-time instead
of the traditional simultaneous booting of all the cores.
Adjust arch_start_cpu() to make that possible.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
To disable the IDC interrupt on the interrupt controller a bit
must be set in the MSD register instead of clearing the bit in
the MCD register, which has no effect.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
irq_enable() should be called with the composite IRQ code as its
argument, not just the Xtensa proper part of it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
BT support requires lots of PROVIDE calls that cannot
be added into this linker file. All necessary includes
were moved into hal module to proper handled as needed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When BT and WiFi coexists, IRAM usage increases a lot.
Add configuration that allow wifi symbols
to be placed in flash, freeing space in IRAM.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
xthal_window_spill call has to be placed into IRAM
in order to allow flash cache disabled operation, otherwise
it will crash.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The sentry symbols that mark the ends of the newlib heap area were
being placed in cached memory, which violates the coherence rules.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Turns out that the user can configure the "zephyr.elf" name via
kconfig to be "something_else.elf" instead. And there's a test the
does this. Use the right variable; don't hardcode.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was added early when we had (somewhat oddly) a log subsystem
backend but not a printk char_out hook. Now we have one backend that
works with both. No need, and this fixes build errors with a handful
of tests that specify LOG_MINIMAL (LOG_PRINTK requires the full log
subsystem and doesn't work with MINIMAL).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
In commit efa05d1e42 ("soc/intel_adsp: Put initial stack into the
CPU0 interrupt stack") the "_end" symbol was accidentally removed from
the linker script. Newlib needs this to size its heap.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The Xtensa L1 cache layer has straightforward semantics accessible via
single-instructions that operate on cache lines via physical
addresses. These are very amenable to inlining.
Unfortunately the Xtensa HAL layer requires function calls to do this,
leading to significant code waste at the calling site, an extra frame
on the stack and needless runtime instructions for situations where
the call is over a constant region that could elide the loop. This is
made even worse because the HAL library is not built with
-ffunction-sections, so pulling in even one of these tiny cache
functions has the effect of importing a 1500-byte object file into the
link!
Add our own tiny cache layer to include/arch/xtensa/cache.h and use
that instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Instead of passing the crt1 _start function as the entry code for
auxiliary CPUs, use a tiny assembly stub instead which can avoid the
runtime testing needed to skip the work in _start. All the crt1 code
was doing was clearing BSS (which must not happen on a second CPU) and
setting the stack pointer (which is wrong on the second CPU).
This allows us to clean out the SMP code in crt1.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Zephyr's normal architecture is to do all initialization in the
interrupt stacks. The CAVS code was traditionally written to start
the stack at the end of HP-SRAM, where it has no protection against
overlap with other uses (e.g. MP startup used the same region for
stacks and saw cache collisions, and the SOF heap lives in this area
too). Put it where Zephyr expects and we'll have fewer surprises.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The kernel passes the CPU's interrupt stack expected that it will
start on that, so do it. Pass the initial stack pointer from the SOC
layer in the variable "z_mp_stack_top" and set it in the assembly
startup before calling z_mp_entry().
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There's no need to muck with the cache directly as long as we're
careful about addressing the shared start record through an uncached
volatile pointer.
Correct a theoretical bug with the initial cache invalidate on the
second CPU which was actually doing a flush (and thus potentially
pushing things the boot ROM wrote into RAM now owned by the OS).
Optimize memory layout a bit when using KERNEL_COHERENCE; we don't
need a full cache line for the start record there as it's already in
uncached memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The multiprocessor entry code here had some bits that look to have
been copied from esp32, including a clumsy stack switch that's needed
there. But it wasn't actually switching the stack at all, which on
this device is pointed at the top of HP-SRAM and can stay there until
the second CPU swaps away into a real thread (this will need to change
once we support >2 CPUS though).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The trace output layer was using this transformation already, make it
an official API. There are other places doing similar logic that can
benefit.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a bunch of dead historical cruft floating around in the
arch/xtensa tree, left over from older code versions. It's time to do
a cleanup pass. This is entirely refactoring and size optimization,
no behavior changes on any in-tree devices should be present.
Among the more notable changes:
+ xtensa_context.h offered an elaborate API to deal with a stack frame
and context layout that we no longer use.
+ xtensa_rtos.h was entirely dead code
+ xtensa_timer.h was a parallel abstraction layer implementing in the
architecture layer what we're already doing in our timer driver.
+ The architecture thread structs (_callee_saved and _thread_arch)
aren't used by current code, and had dead fields that were removed.
Unfortunately for standards compliance and C++ compatibility it's
not possible to leave an empty struct here, so they have a single
byte field.
+ xtensa_api.h was really just some interrupt management inlines used
by irq.h, so fold that code into the outer header.
+ Remove the stale assembly offsets. This architecture doesn't use
that facility.
All told, more than a thousand lines have been removed. Not bad.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Only the CAVS 1.5 linker script has full support for the coherence
features, don't advertise it on the other SoC's yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Glauber Maroto Ferreira