Zephyr kernel masks interrupts before calling the SoC PM
sleep entry point. On the Cortex-Mx family this prevents
wake from peripheral interrupts. The SoC PM layer requires
interrupts to wake the SoC and must prevent the CPU from
vectoring to an interrup until PM exit. The SoC does this
by setting ARM NVIC PRIMASK to 1 and BASEPRI to 0. On
return to the kernel SoC sets PRIMASK to 0 allowing ISR's
to fire. In addition the MEC HW only clears its peripheral
sleep enables if the CPU vectors to an ISR. On wake we
clear the MEC PCR sleep control register which clears all
the peripheral sleep enables so peripherals will be active
before exiting the SoC PM layer.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Change subsystem to use struct pm_state with substate-id instead of
using only the power state category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove conditionals (PM_DEEP_SLEEP_STATES and PM_SLEEP_STATES) from
power management code. Now these features are always available when
power management is enabled.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Migrate the whole pm subsystem to use new power states information
from power_state.h and get states and residency properties from
device tree.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Leftover from old renaming commits. This function is not private and
should not start with underscore.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
z_power_soc_deep_sleep() is called with interrupt locked already
so restoring BASEPRI is pointless here, as it would only allow
exceptions afterwards. The situation is complicated by the fact
that kernel/idle.c:idle() only locks interrupt without unlocking
which means the BASEBRI at entry of z_power_soc_deep_sleep() is
already set to allow exceptions only but not lower priority
interrupts like timer. So when, e.g. timer, interrupt fires,
the SoC would come out of deep sleep but the waking interrupts
are never delivered since they are masked, and idle() will try
to sleep again. And now it gets into a loop of going into deep
sleep briefly and waking up immediately and it goes on and on.
The solution is not to restore BASEPRI and simply leave it at
zero. This is a workaround as a proper fix would involve
invasion changes to the PM subsystem.
Also, _sys_pm_power_state_exit_post_ops() is not being called
when deep sleep is involved, so PRIMASK needs to be reset
after coming out of deep sleep.
Fixes#23274
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The 48MHz PLL on MEC1501 is shut off during deep sleep (i.e. heavy
sleep in datasheet). When coming out of deep sleep, this PLL needs
about 3ms to lock. Most peripherals are using this PLL as clock
source and timing would be off before PLL is locked. Example of
this is seen on serial console where garbage characters are sent
as the UART block is not pushing characters out at the configured
baud rate. This likely affects all other peripherals such as I2C
and eSPI. Luckily, there is a register to indicate whether the PLL
is ready. So spin on it when coming out of deep sleep.
Fixes#23207
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Make sure light sleep hook function is compile when needed
This solves linking error for shippable test that only enable
light sleep.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
When CONFIG_SYS_POWER_DEEP_SLEEP_STATES is not set, we have an unused
function that causes a build failure.
Enclose that function in the #ifdef.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Created MEC1501 deep and light sleep example for MCHP MEC1501.
Modifications were made to SoC, board, timer, and hello world
sample program. Power management split into SoC power
implementing the interface and device power for device specific
logic.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Scott Worley