Commit Graph

2 Commits

Author SHA1 Message Date
Robert Winkler b18309c0d7 boards: doc: Add information about generating litex_vexriscv SoC
This commit adds more information about the litex_vexrscv board
target, including references to related projects and instruction
about generating bitstream for the Digilent Arty A7-35T Board.

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-12-16 12:49:16 -05:00
Nicolas Pitre 1f4b5ddd0f riscv32: rename to riscv
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-02 13:54:48 -07:00