On introduction of a "simplified" HSDK configuration where we only
use 2 cores out of 4 (in assumption that it will be working much
more reliably) we excluded a bit too much of details from OpenOCD script.
In particular we stripped not-used cores from JTAG chain description
which made OpenOCD quite unhappy:
----------------------------->8----------------------------
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: arc-em.cpu2 tap/device found: 0x200c24b1 (mfg: 0x258 (ARC International), part: 0x00c2, ver: 0x2)
Warn : JTAG tap: arc-em.cpu2 UNEXPECTED: 0x200c24b1 (mfg: 0x258 (ARC International), part: 0x00c2, ver: 0x2)
Error: JTAG tap: arc-em.cpu2 expected 1 of 1: 0x200424b1 (mfg: 0x258 (ARC International), part: 0x0042, ver: 0x2)
Info : JTAG tap: arc-em.cpu1 tap/device found: 0x200824b1 (mfg: 0x258 (ARC International), part: 0x0082, ver: 0x2)
Warn : JTAG tap: arc-em.cpu1 UNEXPECTED: 0x200824b1 (mfg: 0x258 (ARC International), part: 0x0082, ver: 0x2)
Error: JTAG tap: arc-em.cpu1 expected 1 of 1: 0x200024b1 (mfg: 0x258 (ARC International), part: 0x0002, ver: 0x2)
Info : JTAG tap: auto0.tap tap/device found: 0x200424b1 (mfg: 0x258 (ARC International), part: 0x0042, ver: 0x2)
Info : JTAG tap: auto1.tap tap/device found: 0x200024b1 (mfg: 0x258 (ARC International), part: 0x0002, ver: 0x2)
Error: Trying to use configured scan chain anyway...
----------------------------->8----------------------------
That lead us to the situation when the target cores were programmed
in a wrong way effectively failing all tests. Fixing it now.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
During review of ARC port of OpenOCD some changes were requested
in particular:
1. L2 cache (SLC in ARC parlance) semantics, see
http://openocd.zylin.com/#/c/5688/
2. JTAG probe interface (AKA "adapter") setup, see
http://openocd.zylin.com/#/c/5784/
And so we need to change OpenOCD scripts accordingly to match
newer OpenOCD version from Zephyr's SDK v0.12.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
add 2 cores configuration for
* who want to use 2 cores
* sanitycheck tests, as we found there are
difference between 2 cores and 4 cores, see
report in issue #26794
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
With latest SDK release v0.11.3 basic SMP support for HSDK
board was introduced in OpenOCD. Lets enable smp in openocd.cfg,
so using west we would be able to run Zephyr on all 4 cores.
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
The last core which gets initilaized is used by default by OpenOCD.
Thus if we leave configuration as it was we'll get single-core
binaries executed by core3 while we expect core0 to be used.
We didn't see that problem reviously because we used to use
GDB for binary (actually Elf) loading and execution and there in GDB
we explicitly connected to the OpenOCD port wired to core 0.
Now with "west flash" we use OpenOCD for loading anr running and
we need everything setup correctly from the beginning.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
To be used in setups with multiple boards attached to the same one
host we need to have an ability to specify precisely which JTAG probe
to use for a particular board.
This is done by passing "ftdi_serial XXX" command to OpenOCD.
And the serial ("XXX") is supposed to be passed from higher level,
typically via west's options.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit includes the initial support of ARC HS Development Kit:
* hsdk soc support
* hsdk board support
* no mmu support, so no userspace
* smp support
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Alexey Brodkin