Commit Graph

5 Commits

Author SHA1 Message Date
Andrew Boie 75caa2b084 arm: exception-assisted kernel panic/oops support
Put the reason code in r0 and make a SVC #2 call, which will be
propagated to _fatal_error_handler as an exception.

The _is_in_isr() implementation had to be tweaked a bit.  User-generated
SVC exception no longer just used for irq_offload(); just because we are
in it does not mean we are in interrupt context.  Instead, have the
irq_offload code set and clear the offload_routine global; it will be
non-NULL only if it's in use. Upcoming changes to support memory
protection (which will require system calls) will need this too.

We free up some small amount of ROM deleting _default_esf struct as it's
no longer needed.

Issue: ZEP-843
Change-Id: Ie82bd708575934cffe41e64f5c128c8704ca4e48
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 10:31:49 -04:00
David B. Kinder ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Anas Nashif c1347b4730 kernel: replace all remaining nanokernel occurances
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.

Keep the legacy samples/tests as is.

Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-25 14:34:43 -05:00
Marcus Shawcroft 362fb9e62b arm: Fix irq offload inline asm memory ordering.
Add a "memory" clobber to inline asm SVC call to ensure the compiler
does not reorder the instruction relative to other memory accesses.

Issue found by inspect the source code.  There is no evidence to
suggest that this bug will manifest for any current ARM target using a
current compiler.

Change-Id: I32b1e5ede02a6dbea02bb8f98729fff1cca1ef2a
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-12-11 11:19:02 +00:00
Andrew Boie bba9510319 irq_offload: API to run a function in IRQ context
Software interrupts or system calls aren't really appropriate for
zephyr, but we have an ongoing need in our test code to run a
function with arguments synchronously in interrupt context.

This patch introduces irq_offload() which allows us to do this without
separate initialization or having to manage fake IRQs in the
interrupt controller.

ARM assembly code contributed by Benjamin Walsh
<benjamin.walsh@windriver.com>

ARC is not yet implemented but will be in a subsequent patch.

irq_test_common.h has been removed and all test cases updated to
use the new API.

Change-Id: I9af99ed31b62bc7eb340e32cf65e3d11354d1ec7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:55 -05:00