We will require 6 variables to be defined by SOC-specific
linker script; these values in turn can be pulled from
defines in layout.h.
To help position code correctly we define two new ELF sections
for this arch, 'reset' and 'exceptions'.
Change-Id: Idffbd53895945b7d0ec0aac281e5bf7c85b4b2c2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This header was pulled in verbatim from Altera HAL and had
some style and naming issues. The inline functions or macros
which read registers can now be used in expressions.
Change-Id: I7a463717051efd2f9dd36e8a84d357852fbf9215
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Nios II has no special instructions for testing bits, ffs, etc.
However, when poking memory-mapped peripherals, special *io variants
of ld and st instructions must be used to avoid issues with the
caches.
find_msb_set / find_lsb_set are implemented using universal GCC
compiler built-ins. It's not clear why this approach was not taken
on other arches.
The sys_in/sys_out/sys_io functions are completely removed as there
is no concept of these on Nios II.
sys_read/sys_write functions implemented using special GCC builtins
for the Nios II so that we don't have to use inline assembly.
Rest of the operations implemented in C, there is no requirement that
they be atomic.
Change-Id: Ic251fc7d7f342543dace4ccb3e429937b303215e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This file is taken verbatim from the Altera Nios II HAL
source and includes various useful processor defines
and macros.
Change-Id: Idbf0b49bebe33bb5a53f5155d927bafadda9a2fe
Origin: nios2.h Altera Nios II HAL
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
BSP builds for Nios II generate a linker.h and system.h which reflects
the configuration for that CPU. This can vary depending on how the CPU
is wired up in QSYS, so it needs to be at the SOC level--we essentially
treat any given CPU configuration as a SOC in Zephyr build terms.
Include these files from <arch/cpu.h>.
Change-Id: I12f76600107fec1a14a2f9cb82b0f55915ec03a6
Origin: Altera Quartus tools, machine generated
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Got lost in the .gitignore when these files had .cmd
extension.
Change-Id: I8a8d51014b621026b739525f3f9a3e8a20cb5ad0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ZEP-252 will handle implementation of the code here.
Change-Id: I3e9a6c7cdf2d5a3b0240317b772628fead528095
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
At the moment this just jumps into prep_c, with comments left
on other things that need to be done. Having this here ensures that
the early boot code isn't discarded by gc-sections.
vector_table.c removed, it isn't the right approach for this CPU.
Proper method for initializing reset and exception vectors still
being investigated.
Change-Id: Id7965c671f1a55c42ecfb65119497405a646bec4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.
This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.
Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Andrew Boie