OrgZephyr/zephyr
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Author SHA1 Message Date
Filip Kokosinski 342cbc9e01 soc: riscv32: add LiteX VexRiscV SoC 
Add LiteX with softcore CPU VexRiscV SoC definitions and default
configurations.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
 2019-05-15 12:52:16 -05:00