Commit Graph

7 Commits

Author SHA1 Message Date
Andrew Boie 6fd6b7e50a xtensa: remove legacy arch implementation
We re-wrote the xtensa arch code, but never got around
to purging the old implementation.

Removed those boards which hadn't been moved to the new
arch code. These were all xt-sim simulator targets and not
real hardware.

Fixes: #18138

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-12 01:26:34 -04:00
Anas Nashif 3ae52624ff license: cleanup: add SPDX Apache-2.0 license identifier
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier.  Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.

By default all files without license information are under the default
license of Zephyr, which is Apache version 2.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-07 08:45:22 -04:00
Andy Ross 392b3b5aa6 xtensa/asm2: Don't needlessly build asm2 sources
Non-asm2 devices without a generated SoC interrupt file will see a
compile failure due to the missing header.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross c761ae9695 xtensa: Add Kconfig for asm2 layer
The asm2 layer will build alongside the traditional assembly, but the
reverse is not true.  Add a CONFIG_XTENSA_ASM2 to force its use at
runtime and disable the older code.

Note that the older assembly had an initialization function that is
properly part of the timer driver.  Move a C equivalent into the timer
driver itself for now to prevent a build breakage.  Long term we need
to clean that driver up in a bunch of other ways.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross a34f884f23 xtensa: New asm layer to support SMP
SMP needs a new context switch primitive (to disentangle _swap() from
the scheduler) and new interrupt entry behavior (to be able to take a
global spinlock on behalf of legacy drivers).  The existing code is
very obtuse, and working with it led me down a long path of "this
would be so much better if..."  So this is a new context and entry
framework, intended to replace the code that exists now, at least on
SMP platforms.

New features:

* The new context switch primitive is xtensa_switch(), which takes a
  "new" context handle as an argument instead of getting it from the
  scheduler, returns an "old" context handle through a pointer
  (e.g. to save it to the old thread context), and restores the lock
  state(PS register) exactly as it is at entry instead of taking it as
  an argument.

* The register spill code understands wrap-around register windows and
  can avoid spilling A4-A15 registers when they are unused by the
  interrupted function, saving as much as 48 bytes of stack space on
  the interrupted stacks.

* The "spill register windows" routine is entirely different, using a
  different mechanism, and is MUCH FASTER (to the tune of almost 200
  cycles).  See notes in comments.

* Even better, interrupt entry can be done via a clever "cross stack
  call" I worked up, meaning that the interrupted thread's registers
  do not need to be spilled at all until they are naturally pushed out
  by the interrupt handler or until we return from the interrupt into
  a different thread.  This is a big efficiency win for tiny
  interrupts (e.g. timers), and a big latency win for all interrupts.

* Interrupt entry is 100% symmetric with respect to medium/high
  interrupts, avoiding the problems seen with hooking high priority
  interrupts with the current code (e.g. ESP-32's watchdog driver).

* Much smaller code size.  No cut and paste assembly.  No use of HAL
  calls.

* Assumes "XEA2" interrupt architecture, the register window extension
  (i.e. no CALL0 ABI), and the "high priority interrupts" extension.
  Does not support the legacy processor variants for which we have no
  targets.  The old code has some stuff in there to support this, but
  it seems bitrotten, untestable, and I'm all but certain it doesn't
  work.

Note that this simply adds the primitives to the existing tree in a
form where they can be unit tested.  It does not replace the existing
interrupt/exception handling or _Swap() implementation.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 88538e77c1 xtensa: Move register window exception handlers into a separate file
No behavior changes, just code motion.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Sebastian Bøe 12f8f76165 Introduce cmake-based rewrite of KBuild
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.

Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.

This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.

For users that just want to continue their work with minimal
disruption the following should suffice:

Install CMake 3.8.2+

Port any out-of-tree Makefiles to CMake.

Learn the absolute minimum about the new command line interface:

$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..

$ cd build
$ make

PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html

Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00