Commit Graph

6 Commits

Author SHA1 Message Date
Ramakrishna Pallala 3a8e37caae soc: x86: quark_se: Select the supported Power States
Select the Low Power States supported by Intel Quark SE SoC series.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-09-28 06:54:15 +05:30
Maureen Helm 0be600016c soc: x86: arc: Remove spi base address and irq macros
Now that we get the spi base address and irq numbers from dts, we can
remove the preprocessor macros from soc.h

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-28 06:27:06 +05:30
Maureen Helm 55caa7b743 drivers: spi: Select HAS_DTS_SPI in designware driver
Makes the designware spi driver consistent with other spi drivers by
selecting HAS_DTS_SPI in the driver. This required adding spi nodes and
dts fixups to several arc and x86 socs, as well as enabling those nodes
in associated boards.

Also refactors the driver to use the base address, interrupt number, and
interrupt priority from dts.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-28 06:27:06 +05:30
Daniel Leung 8d18ebde9b gpio: add driver for Intel Apollo Lake SoC
This adds a driver for GPIO controller on the Intel
Apollo Lake SoC.

Origin: Original

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-19 21:36:16 -04:00
Kumar Gala e4a96ccbc4 dts: Cleanup warnings associated with unit_address_format and leading 0s
We get several warnings of the form:

	Warning (unit_address_format): /soc/uart@000003f8:
	unit name should not have leading 0s

Fix these by remove the leading 0s.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-09-18 10:43:58 -07:00
Anas Nashif cff0005a87 x86: move soc/cpu to top-level under soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00