Added test suite which performs sanity check on instances with
fixed-top feature enabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Added tests which verifies that:
- driver will detect when absolute alarm is set too late.
- short relative alarm is supported
- canceled alarm is not triggering user callback
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
PPI allocation and freeing was not handled correctly. Additionally,
RTC event was not enabled when PPI was enabled which resulted in
lack of RTC counter clearing.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Implemented latest extensions to the counter API related to
detection of alarms being set too late and short relative alarms.
Implementation could not be realized on nrfx_rtc driver thus
driver has been reimplemented based on nrf_rtc hal.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Implemented latest extensions to the counter API related to
detection of alarms being set too late and short relative alarms.
Implementation could not be realized on nrfx_timer driver thus
driver has been reimplemented based on nrf_timer hal.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Fix ticker previous slot value with elapsed ticks value from
the time stopped ticker has expired. When a ticker is
stopped, if it was in its reserved time space, then the
currently occupied slot (was set to 0) should be the amount
of time that has elapsed in the expired and stopped ticker's
reserved time space and beyond until the stop.
This is required to ensure that any other new ticker does
not get scheduled over the stopped ticker's reserved time
space.
Fixes#19515.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Add support for Zero Latency IRQs, which avoids any Zephyr
OS or application influenced ISR latencies on the
controller's ISRs.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Add support for Zero Latency IRQs, which avoids any Zephyr
OS or application influenced ISR latencies on the
controller's ISRs.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
The patch adds initial support for STM32F030X4 SoC.
STM32F0 Cube package advises to use 'stm32f030x6' code
for both STM32F030x4 and STM32F030x6 SoC variants.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Revert 1b5e6072ca which
broke things for off-tree toolchains,
and add a note about the reason for that line so it is not
removed again.
That include line is, logically, not there for the compilers which
are supported in the tree, but for other compilers which would
be supported thru off-tree headers and cmake files.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Add in-line documentation describing the process of register
preservation and exception handling on Cortex-R.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The interrupt exit and swap service routines for Cortex-R
unnecessarily preserve r0 and lr registers when making function calls
using bl instruction.
In case of _IntExit in exc_exit.S, the r0 register containing the
caller mode is preserved at the top, and the lr register can safely be
assumed to have been saved into the system mode stack by the interrupt
service routine.
In case of __svc in swap_helper.S, since the function saves lr to the
system mode stack at the top and exits through _IntExit, it is not
necessary to preserve lr register when executing bl instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Updated connection info and restructered a bit some paragraphs to stay
consistent with the structure of other boards.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
found some references to files (via :zephyr_file: and :zephyr-app:) that
were moved, so the links were broken
Fixes: #19660
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
The driver fails to compile when CONFIG_UART_INTERRUPT_DRIVEN=n. This is
due to a nested ifdef on CONFIG_UART_INTERRUPT_DRIVEN that is excluding
pieces of code unrelated to the uart interrupts management.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The PL011 driver is not specific to the cortex_m arch and the driver
does not really use anything from the cmsis header file. Remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Creates macros for determining model message lengths based on opcode,
payload length and MIC size. Also adds macro wrapping
NET_BUF_SIMPLE_DEFINE to serve the most common use case.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
DTSpec writes this as a single word, presumably to make it easier to
grep for / more precise. Follow along in the rest of the docs now that
our main DT docs page agrees with this usage.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
The K6X example is part of the wrong subsection (devicetree vs
kconfig) currently. Move it up to the right place (the section which
was recently renamed to "input and output files")
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Re-work the introductory sections of the devicetree documentation,
adding several figures and cross-references to other useful parts of
the documentation.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Device tree overlays are a bit of a stumbling block. Try to add more
cross-references and examples for how to use them to the application
development doc and the west build page.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
When running a ticker node as "must expire", the node would invoke the
ticker callback even when programmed with latency. As "must expire" is
intended for scheduled events which are skipped due to collision, and as
such expected by LLL, purposefully skipped events should not generate
"must expire" callbacks.
Signed-off-by: Morten Priess <mtpr@oticon.com>
Fixes u32_t overflow during intermediary calculations using u64_t for
it. on_off is temporary value used for calculating on and off and it
got overflowed with simple test in tests/drivers/pwm/pwm_api
([period]: 2000, [pulse]: 2000)
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
It is now possible to override a shield variant configuration
for a specific board. Get it documented.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Shields subsystem provides the possibility to override configuration
for boards and to define variants.
Reflect this in documentation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Just housekeeping around the casting between void * arguments to
thread functions and integer types.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
It's possible to have multiple processors configured without using the
SMP scheduler, so don't make definitions dependent on CONFIG_SMP.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
In non-SMP MP situations, the interrupt stacks might not exist, so
do not assume they do. Instead, initialize the TSS IST1 from the
cpuboot[] vector (meaning, on APs, the stack from z_arch_start_cpu).
Eliminates redundancy at the same time.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
When SMP is enabled, the kernel expects that interrupts be delivered
to all CPUs in the system. Change the I/O APIC RTEs accordingly.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This is the Wrong Thing(tm) with SMP enabled. Previously this
worked because interrupts would be re-enabled in the interrupt
entry sequence, but this is no longer the case.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
was ignoring the rest of the expression, though the effect was
harmless (including unreachable code in some builds).
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Trivial change to the Kconfig: the first 32 vectors are reserved,
so it's not possible to have 256 IRQ vectors. Change max to 224.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add duplicate per-CPU data structures (x86_cpuboot, tss, stacks, etc.)
for up to 4 total CPUs, add code in locore and z_arch_start_cpu().
The test board, qemu_x86_long, now defaults to 2 CPUs.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Take a dummy first argument, so that the BSP entry point (z_x86_prep_c)
has the same signature as the AP entry point (smp_init_top).
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add a simple inline function and some definitions to faciliate
inter-processor interrupts for SMP initialization/synchronization.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Krzysztof Chruscinski