Made sram0 visible for NETWORK core target. The core might
access sram0 as shared region might be defined inside it.
Made sram1 visible for APPLICATION core target for keeping
consistence.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
In the SoC that comes on the nRF5340 DK the number of MPU
regions in the nRF5340 Network MCU is 8, instead of 16. We
fix this in DTS by introducing different .dtsi headers for the
different SoC part variants: the nrf340 Engineering A (first
SoC revision, present in the nRF5340 PDK) and the nrf5340
(second SoC revision, present on nRF5340 DK).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We need to use CPUAPP and CPUNET instead of CPU0 and CPU1
terminology, because those terms are the ones used
throughout the DeviceTree definitions for nRF5340 SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Andrzej Puzdrowski