Upgrade board specification to use the VirtIO board.
Keeps FPU run-time support disabled since the RISC-V 64-bit FPU
support in kernel appears to be non-functional.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Instead of endlessly repeating the same command line args,
centralize this and tune the shift value on a per-board
basis.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Enable icount mode for qemu_riscv64 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board.
Memory is tight so a few tests had to be disabled due to the extra
memory usage compared to qemu_riscv32.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Martin Åberg