Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This will replace the current goal of 'make qemu' with 'make run' and
moves Qemu handling into its own file and into the boards instead of
being architecture specific.
We should be able to add new boards that support some other type of
emulation (by adding scripts/Makefile.<emu type>) and allow the board to
define their own options for the use type of emulation.
'make qemu' will still work, however it will be deprecated, starting
with this commit it is recommended to use 'make run'.
Jira: ZEP-359
Change-Id: I1cacd56b4ec09421a58cf5d010e22e9035214df6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit replaces the x86 asm line:
__asm__ __volatile__ ("bswap %0" : "=r" (x) : "0" (x));
by the sys_cpu_to_be32 macro.
By removing the x86 asm instruction, the nfc_hello sample app
can run on other platforms.
Jira: ZEP-1348
Change-Id: I440e96cd06e70a88552d179a2288c9918e6ca0b0
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
Remove those from Makefiles and testcase.ini, we now support unified kernel
only and sanitycheck script now knows how to deal with this.
Change-Id: I853ebcadfa7b56a4de5737d95f2ba096babb2e13
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The old 'config_whitelist' directive in testcase.ini has been removed.
We use the new expr_parser module to parse a 'filter' directive which
is a boolean expression. This gives a great deal more flexibility
in how tests can be filtered.
To keep the tree bisectable, use of config_whitelist in testcase.ini
converted to the new expression language.
Change-Id: I0617319818c5559c0f0569d2fa73d09b681cac51
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.
Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.
This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.
Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.
This also addresses the following issues:
() UART driver for Atmel SAM3 currently does not support interrupts.
So remove the code from vector table. This will be updated when
there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.
This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).
Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This sample goes under samples/nfc directory where we will
have all nfc related samples.
Change-Id: I6e7664d8e0dcbfcb0d9e11e2c7b79d8217665757
Signed-off-by: Anas Nashif <anas.nashif@intel.com>